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15 条记录 (耗时 0.036 秒)

    BiCMOS integration scheme with raised extrinsic base
    1.
    发明授权
    BiCMOS integration scheme with raised extrinsic base 有权
    BiCMOS整合方案具有突出的外在基础

    公开(公告)号：US06780695B1

    公开(公告)日：2004-08-24

    申请号：US10249563

    申请日：2003-04-18

    申请人： Huajie Chen ,  Seshadri Subbanna ,  Basanth Jagannathan ,  Gregory G. Freeman ,  David C. Ahlgren ,  David Angell ,  Kathryn T. Schonenberg ,  Kenneth J. Stein ,  Fen F. Jamin

    发明人： Huajie Chen ,  Seshadri Subbanna ,  Basanth Jagannathan ,  Gregory G. Freeman ,  David C. Ahlgren ,  David Angell ,  Kathryn T. Schonenberg ,  Kenneth J. Stein ,  Fen F. Jamin

    IPC分类号： H01L218238

    CPC分类号： H01L21/8249 ,  H01L27/0623

    摘要： A method of forming a BiCMOS integrated circuit having a raised extrinsic base is provided. The method includes first forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate having device areas for forming at least one bipolar transistor and device areas for forming at least one complementary metal oxide semiconductor (CMOS) transistor. The polysilicon layer is then patterned to provide a sacrificial polysilicon layer over the device areas for forming the at least one bipolar transistor and its surrounding areas, while simultaneously providing at least one gate conductor in the device areas for forming at least one CMOS transistor. At least one pair of spacers are then formed about each of the at least one gate conductor and then a portion of the sacrificial polysilicon layer over the bipolar device areas are selectively removed to provide at least one opening in the bipolar device area. At least one bipolar transistor having a raised extrinsic base is then formed in the at least one opening.

    摘要翻译： 提供一种形成具有凸起的外在基极的BiCMOS集成电路的方法。 该方法包括首先在位于具有用于形成至少一个双极晶体管的器件区域的衬底的顶部的栅极电介质的表面上方形成多晶硅层，以及用于形成至少一个互补金属氧化物半导体（CMOS）晶体管的器件区域）。 然后将多晶硅层图案化以在器件区域上提供用于形成至少一个双极晶体管及其周围区域的牺牲多晶硅层，同时在用于形成至少一个CMOS晶体管的器件区域中提供至少一个栅极导体。 然后围绕至少一个栅极导体的每一个形成至少一对间隔物，然后选择性地去除双极器件区域上的牺牲多晶硅层的一部分以在双极器件区域中提供至少一个开口。 然后在至少一个开口中形成至少一个具有凸起的非本征基极的双极晶体管。

    In-situ monitoring and control of germanium profile in silicon-germanium alloy films and temperature monitoring during deposition of silicon films
    3.
    发明授权
    In-situ monitoring and control of germanium profile in silicon-germanium alloy films and temperature monitoring during deposition of silicon films 失效
    原位监测和控制硅锗合金薄膜中的锗分布以及淀积硅膜期间的温度监测

    公开(公告)号：US06881259B1

    公开(公告)日：2005-04-19

    申请号：US09633857

    申请日：2000-08-07

    申请人： David C. Ahlgren ,  Jack Oon Chu ,  Basanth Jagannathan ,  Ryan W. Wuthrich

    发明人： David C. Ahlgren ,  Jack Oon Chu ,  Basanth Jagannathan ,  Ryan W. Wuthrich

    IPC分类号： C30B25/16 ,  C30B29/52

    CPC分类号： C30B29/52 ,  C30B25/165

    摘要： Analysis of residual gases from a process for depositing a film containing silicon on a crystalline silicon surface to determine partial pressure of hydrogen evolved during deposition develops a signature which indicates temperature and/or concentration of germanium at the deposition surface. Calibration and collection of hydrogen partial pressure data at a rate which is high relative to film deposition rate allows real-time, in-situ, non-destructive determination of material concentration profile over the thickness of the film and/or monitoring the temperature of a silicon film deposition process with increased accuracy and resolution to provide films of a desired thickness with high accuracy.

    摘要翻译： 分析来自用于在晶体硅表面上沉积含硅的膜的工艺的残余气体，以确定在沉积期间释放出来的氢的分压，形成指示沉积表面的锗的温度和/或浓度的标记。 以相对于膜沉积速率高的速率校准和收集氢分压数据允许在膜的厚度上的材料浓度分布的实时，原位，非破坏性测定和/或监测膜的温度 硅膜沉积工艺具有更高的精度和分辨率，以高精度提供所需厚度的膜。

    Bipolar transistor with raised extrinsic base fabricated in an integrated BiCMOS circuit
    9.
    发明授权
    Bipolar transistor with raised extrinsic base fabricated in an integrated BiCMOS circuit 有权
    具有凸起的外部基极的双极晶体管在集成的BiCMOS电路中制造

    公开(公告)号：US06492238B1

    公开(公告)日：2002-12-10

    申请号：US09887310

    申请日：2001-06-22

    申请人： David C. Ahlgren ,  Gregory G. Freeman ,  Feng-Yi Huang ,  Adam D. Ticknor

    发明人： David C. Ahlgren ,  Gregory G. Freeman ,  Feng-Yi Huang ,  Adam D. Ticknor

    IPC分类号： H01L2100

    CPC分类号： H01L29/66287 ,  H01L21/8249 ,  H01L27/0623

    摘要： A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.

    摘要翻译： 用于形成具有凸起的外部基极，发射极和与具有栅极的CMOS电路集成的集电极的双极晶体管的工艺。 提供具有CMOS和双极区域的中间半导体结构。 在双极区域内提供本征基层。 基底氧化物跨越形成，牺牲发射极堆叠硅层沉积在CMOS和双极区两者上。 施加光致抗蚀剂以保护双极区域，并且蚀刻该结构以从CMOS区域去除牺牲层，使得双极区域上的牺牲层的顶表面基本上与CMOS区域的顶表面齐平。 最后，沉积抛光停止层，其具有穿过适于随后的化学机械抛光（CMP）的CMOS和双极区域的基本平坦的顶表面，以形成凸起的外在基体。

    Fully silicided extrinsic base transistor
    10.
    发明授权
    Fully silicided extrinsic base transistor 失效
    全硅化外基晶体管

    公开(公告)号：US07585740B2

    公开(公告)日：2009-09-08

    申请号：US11308259

    申请日：2006-03-14

    申请人： David C. Ahlgren ,  Guy M. Cohen ,  Christian Lavoie ,  Francois Pagette ,  Anna W. Topol

    发明人： David C. Ahlgren ,  Guy M. Cohen ,  Christian Lavoie ,  Francois Pagette ,  Anna W. Topol

    IPC分类号： H01L21/331

    CPC分类号： H01L29/1004 ,  H01L29/1608 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7378

    摘要： A system and method comprises forming an intrinsic base on a collector. The system and method further includes forming a fully silicided extrinsic base on the intrinsic base by a self-limiting silicidation process at a predetermined temperature and for a predetermined amount of time, the silicidation substantially stopping at the intrinsic base. The system and method further includes forming an emitter which is physically insulated from the extrinsic base and the collector, and which is in physical contact with the intrinsic base.

    摘要翻译： 一种系统和方法包括在收集器上形成固有碱基。 该系统和方法还包括通过在预定温度下的自限硅化工艺在本征基底上形成完全硅化的外在碱，并且预定量的时间，硅化物在本征碱基本上停止。 该系统和方法还包括形成与外部基极和集电器物理绝缘的发射极，并与内部基极物理接触。