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    Processor voltage regulation
    1.
    发明授权
    Processor voltage regulation 有权
    处理器电压调节

    公开(公告)号：US08812879B2

    公开(公告)日：2014-08-19

    申请号：US12650516

    申请日：2009-12-30

    申请人： Huajun Wen ,  Joshua D. Friedrich ,  Norman K. James ,  Seongwon Kim ,  John R. Ripley ,  Edmund J. Sprogis

    发明人： Huajun Wen ,  Joshua D. Friedrich ,  Norman K. James ,  Seongwon Kim ,  John R. Ripley ,  Edmund J. Sprogis

    IPC分类号： G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/3203 ,  G05F1/56 ,  G06F1/26 ,  G06F1/3287 ,  Y02D10/171

    摘要： A voltage regulator module (VRM) includes a first interface configured to couple to a first substrate interface at a first voltage. The VRM also includes a second interface configured to couple to a first processor interface at a second voltage. A first regulator module couples to the first interface and to the second interface. The first regulator module is configured to receive power at the first interface, to convert power to the second voltage, and to deliver power to the first processor interface at the second voltage. A method for providing power to a processor includes receiving power from a first substrate interface at a first voltage. The received power is regulated to generate power at a second voltage. The regulated power is provided to a processor at a first processor interface coupled to the processor. The processor interface delivers power to a logic group of a plurality of logic groups of the processor.

    摘要翻译： 电压调节器模块（VRM）包括被配置为以第一电压耦合到第一衬底接口的第一接口。 VRM还包括被配置为以第二电压耦合到第一处理器接口的第二接口。 第一调节器模块耦合到第一接口和第二接口。 第一调节器模块被配置为在第一接口处接收电力，以将功率转换为第二电压，并且以第二电压将功率输送到第一处理器接口。 向处理器提供电力的方法包括以第一电压从第一基板接口接收功率。 接收的功率被调节以在第二电压下产生功率。 将调节的功率提供给耦合到处理器的第一处理器接口处的处理器。 处理器接口向处理器的多个逻辑组的逻辑组递送电力。

    PROCESSOR VOLTAGE REGULATION
    2.
    发明申请
    PROCESSOR VOLTAGE REGULATION 有权
    处理器电压调节

    公开(公告)号：US20110161682A1

    公开(公告)日：2011-06-30

    申请号：US12650516

    申请日：2009-12-30

    申请人： Huajun Wen ,  Joshua D. Friedrich ,  Norman K. James ,  Seongwon Kim ,  John R. Ripley ,  Edmund J. Sprogis

    发明人： Huajun Wen ,  Joshua D. Friedrich ,  Norman K. James ,  Seongwon Kim ,  John R. Ripley ,  Edmund J. Sprogis

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3203 ,  G05F1/56 ,  G06F1/26 ,  G06F1/3287 ,  Y02D10/171

    摘要： A voltage regulator module (VRM) includes a first interface configured to couple to a first substrate interface at a first voltage. The VRM also includes a second interface configured to couple to a first processor interface at a second voltage. A first regulator module couples to the first interface and to the second interface. The first regulator module is configured to receive power at the first interface, to convert power to the second voltage, and to deliver power to the first processor interface at the second voltage. A method for providing power to a processor includes receiving power from a first substrate interface at a first voltage. The received power is regulated to generate power at a second voltage. The regulated power is provided to a processor at a first processor interface coupled to the processor. The processor interface delivers power to a logic group of a plurality of logic groups of the processor.

    摘要翻译： 电压调节器模块（VRM）包括被配置为以第一电压耦合到第一衬底接口的第一接口。 VRM还包括被配置为以第二电压耦合到第一处理器接口的第二接口。 第一调节器模块耦合到第一接口和第二接口。 第一调节器模块被配置为在第一接口处接收电力，以将功率转换为第二电压，并且以第二电压将功率输送到第一处理器接口。 向处理器提供电力的方法包括以第一电压从第一基板接口接收功率。 接收的功率被调节以在第二电压下产生功率。 将调节的功率提供给耦合到处理器的第一处理器接口处的处理器。 处理器接口向处理器的多个逻辑组的逻辑组递送电力。

    Internally Controlling and Enhancing Logic Built-In Self Test in a Multiple Core Microprocessor
    5.
    发明申请
    Internally Controlling and Enhancing Logic Built-In Self Test in a Multiple Core Microprocessor 失效
    在多核微处理器中内部控制和增强逻辑内置自检

    公开(公告)号：US20100262879A1

    公开(公告)日：2010-10-14

    申请号：US12423442

    申请日：2009-04-14

    申请人： Michael S. Floyd ,  Joshua D. Friedrich ,  Robert B. Gass ,  Norman K. James

    发明人： Michael S. Floyd ,  Joshua D. Friedrich ,  Robert B. Gass ,  Norman K. James

    IPC分类号： G01R31/3177 ,  G06F11/25

    CPC分类号： G01R31/3187 ,  G01R31/31724 ,  G06F11/27

    摘要： A mechanism is provided for internally controlling and enhancing logic built-in self test in a multiple core microprocessor. The control core may use architectural support for scan and external scan communication (XSCOM) to independently test the other cores while adjusting their frequency and/or voltage. A program loaded onto the control core may adjust the frequency and configure the LBIST to run on each of the cores under test. Once LBIST has completed on a core under test, the control core's program may evaluate the results and decide a next test to run for that core. For isolating failing latch positions, the control core may iteratively configure the LBIST mask and sequence registers on the core under test to determine the location of the failing latch. The control core may control the LBIST stump masks to isolate the failure to a particular latch scan ring and then position within that ring.

    摘要翻译： 提供了一种用于在多核微处理器内部控制和增强逻辑内置自检的机制。 控制核心可以使用架构支持扫描和外部扫描通信（XSCOM）来独立测试其他内核，同时调整其频率和/或电压。 加载到控制核心上的程序可以调整频率并配置LBIST以在被测试的每个核心上运行。 一旦LBIST已经在被测核心上完成，控制核心的程序可以评估结果并决定下一个测试以运行该核心。 为了隔离失效的锁存位置，控制核可以迭代地配置待测核心上的LBIST掩码和序列寄存器，以确定故障锁存器的位置。 控制核心可以控制LBIST残端掩模以将故障隔离到特定的锁存扫描环，然后位于该环内。

    Internally controlling and enhancing logic built-in self test in a multiple core microprocessor
    6.
    发明授权
    Internally controlling and enhancing logic built-in self test in a multiple core microprocessor 失效
    在多核微处理器中内部控制和增强逻辑内置自检

    公开(公告)号：US08122312B2

    公开(公告)日：2012-02-21

    申请号：US12423442

    申请日：2009-04-14

    申请人： Michael S. Floyd ,  Joshua D. Friedrich ,  Robert B. Gass ,  Norman K. James

    发明人： Michael S. Floyd ,  Joshua D. Friedrich ,  Robert B. Gass ,  Norman K. James

    IPC分类号： G01R31/28

    CPC分类号： G01R31/3187 ,  G01R31/31724 ,  G06F11/27

    摘要： A mechanism is provided for internally controlling and enhancing logic built-in self test in a multiple core microprocessor. The control core may use architectural support for scan and external scan communication (XSCOM) to independently test the other cores while adjusting their frequency and/or voltage. A program loaded onto the control core may adjust the frequency and configure the LBIST to run on each of the cores under test. Once LBIST has completed on a core under test, the control core's program may evaluate the results and decide a next test to run for that core. For isolating failing latch positions, the control core may iteratively configure the LBIST mask and sequence registers on the core under test to determine the location of the failing latch. The control core may control the LBIST stump masks to isolate the failure to a particular latch scan ring and then position within that ring.

    摘要翻译： 提供了一种用于在多核微处理器内部控制和增强逻辑内置自检的机制。 控制核心可以使用架构支持扫描和外部扫描通信（XSCOM）来独立测试其他内核，同时调整其频率和/或电压。 加载到控制核心上的程序可以调整频率并配置LBIST以在被测试的每个核心上运行。 一旦LBIST已经在被测核心上完成，控制核心的程序可以评估结果并决定下一个测试以运行该核心。 为了隔离失效的锁存位置，控制核可以迭代地配置待测核心上的LBIST掩码和序列寄存器，以确定故障锁存器的位置。 控制核心可以控制LBIST残端掩模以将故障隔离到特定的锁存扫描环，然后位于该环内。

    Dynamic Frequency And Voltage Scaling For A Computer Processor
    7.
    发明申请
    Dynamic Frequency And Voltage Scaling For A Computer Processor 审中-公开
    用于计算机处理器的动态频率和电压调节

    公开(公告)号：US20100094572A1

    公开(公告)日：2010-04-15

    申请号：US12251891

    申请日：2008-10-15

    申请人： Harold W. Chase ,  Joshua D. Friedrich ,  Soraya Ghiasi ,  Norman K. James ,  Jagat V. Pokala

    发明人： Harold W. Chase ,  Joshua D. Friedrich ,  Soraya Ghiasi ,  Norman K. James ,  Jagat V. Pokala

    IPC分类号： G06F19/00 ,  G06F1/26

    CPC分类号： G06F1/3203 ,  Y02D10/126

    摘要： Methods, apparatus, and computer program products are described for dynamic frequency and voltage scaling for a computer processor, including identifying during manufacture a nominal operating point of frequency and voltage for a computer processor, the nominal operating point including a nominal operating voltage identified for a design nominal operating frequency; determining, in dependence upon the nominal operating point, an operating range of frequency and voltage over which the computer processor is to function; and storing, in non-volatile storage on the computer processor during manufacture, information specifying the nominal operating point and the operating range.

    摘要翻译： 描述了用于计算机处理器的动态频率和电压缩放的方法，装置和计算机程序产品，包括在制造期间识别计算机处理器的频率和电压的标称工作点，标称工作点包括为 设计标称工作频率; 根据标称工作点确定计算机处理器将在其上工作的频率和电压的工作范围; 并且在制造期间在计算机处理器的非易失性存储器中存储指定标称工作点和操作范围的信息。

    DUTY CYCLE MEASURMENT CIRCUIT FOR MEASURING AND MAINTAINING BALANCED CLOCK DUTY CYCLE
    8.
    发明申请
    DUTY CYCLE MEASURMENT CIRCUIT FOR MEASURING AND MAINTAINING BALANCED CLOCK DUTY CYCLE 审中-公开
    用于测量和维护平衡时间周期的占空比测量电路

    公开(公告)号：US20080198700A1

    公开(公告)日：2008-08-21

    申请号：US12045059

    申请日：2008-03-10

    申请人： Robert L. Franch ,  William V. Huott ,  Norman K. James ,  Phillip J. Restle ,  Timothy M. Skergan

    发明人： Robert L. Franch ,  William V. Huott ,  Norman K. James ,  Phillip J. Restle ,  Timothy M. Skergan

    IPC分类号： G04F10/00

    CPC分类号： G01R31/31725 ,  G01R31/318594

    摘要： A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.

    摘要翻译： 用于测量时钟数字路径中的定时不确定度的电路，特别是在任何时钟周期内完成的逻辑级数。 本地时钟缓冲器接收全局时钟并提供互补的本地时钟对。 第一本地（发射）时钟是延迟线的输入，例如，3个时钟周期的串联逆变器。 延迟线抽头（逆变器输出）是由互补时钟对计时的寄存器的输入，以通过延迟线捕获启动时钟的进程，并识别出该进程中的任何变化（例如抖动，VDD噪声）。 可以通过来自一对这样的时钟缓冲器的交叉耦合启动时钟来测量全局时钟偏移和跨芯片栅极长度变化，并且选择性地将本地和远程启动时钟传递到相应的延迟线。

    Internally controlling and enhancing advanced test and characterization in a multiple core microprocessor
    10.
    发明授权
    Internally controlling and enhancing advanced test and characterization in a multiple core microprocessor 失效
    在多核微处理器内部控制和增强先进的测试和表征

    公开(公告)号：US08140902B2

    公开(公告)日：2012-03-20

    申请号：US12269490

    申请日：2008-11-12

    申请人： Michael S. Floyd ,  Robert B. Gass ,  Norman K. James

    发明人： Michael S. Floyd ,  Robert B. Gass ,  Norman K. James

    IPC分类号： G06F11/00

    CPC分类号： G06F11/2242

    摘要： A mechanism is provided for internally controlling and enhancing advanced test and characterization in a multiple core microprocessor. To decrease the time needed to test a multiple core chip, the mechanism uses micro-architectural support that allows one core, a control core, to run a functional program to test the other cores. Any core on the chip can be designated to be the control core as long as it has already been tested for functionality at one safe frequency and voltage operating point. An external testing device loads a small program into the control core's dedicated memory. The program functionally running on the control core uses micro-architectural support for functional scan and external scan communication to independently test the other cores while adjusting the frequencies and/or voltages of the other cores until failure. The control core may independently test the other cores by starting, stopping, and determining pass/fail results.

    摘要翻译： 提供了一种用于内部控制和增强多核微处理器中的高级测试和表征的机制。 为了减少测试多核芯片所需的时间，该机制使用微架构支持，允许一个核心（控制核心）运行功能程序来测试其他内核。 只要在一个安全频率和电压工作点已经测试了功能，芯片上的任何内核都可以被指定为控制核心。 外部测试设备将一个小程序加载到控制核心的专用存储器中。 在控制核心上运行的程序使用微架构支持功能扫描和外部扫描通信，以独立测试其他内核，同时调整其他内核的频率和/或电压直到故障。 控制核心可以通过启动，停止和确定通过/失败结果来独立测试其他内核。