公开(公告)号：US20090162981A1

公开(公告)日：2009-06-25

申请号：US12372541

申请日：2009-02-17

申请人： Huaxiang YIN ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-young Kim

发明人： Huaxiang YIN ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-young Kim

IPC分类号： H01L21/84

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/7855

摘要： A thin film transistor and a method of manufacturing the same are provided. The thin film transistor includes a substrate; a buffer layer formed on the substrate; a source and a drain spaced apart from each other on the buffer layer; a channel layer formed on the buffer layer to connect the source and the drain with each other; and a gate formed on the buffer layer to be spaced apart from the source, the drain and the channel layer.

摘要翻译： 提供薄膜晶体管及其制造方法。 薄膜晶体管包括基板; 形成在所述基板上的缓冲层; 在缓冲层上彼此间隔开的源极和漏极; 形成在所述缓冲层上的沟道层，以将所述源极和所述漏极彼此连接; 以及形成在缓冲层上以与源极，漏极和沟道层间隔开的栅极。

公开(公告)号：US20060267100A1

公开(公告)日：2006-11-30

申请号：US11430117

申请日：2006-05-09

申请人： Takashi Noguchi ,  Hans Cho ,  Wenxu Xianyu ,  Do-young Kim ,  Jang-yeong Kwon ,  Huaxiang Yin ,  Kyung-bae Park ,  Xiaozin Zhang

发明人： Takashi Noguchi ,  Hans Cho ,  Wenxu Xianyu ,  Do-young Kim ,  Jang-yeong Kwon ,  Huaxiang Yin ,  Kyung-bae Park ,  Xiaozin Zhang

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7842 ,  Y10S257/903

摘要： A semiconductor device including a substrate, a P-MOS single crystal TFT formed on the substrate, and an N-MOS single crystal TFT formed on the P-MOS single crystal TFT. The source region of the P-MOS single crystal TFT and the source region of the N-MOS single crystal TFT may be connected to each other. The P-MOS single crystal TFT and the N-MOS single crystal TFT may share a common gate. Also, the P-MOS single crystal TFT may include a single crystal silicon layer with a crystal plane of (100) and a crystal direction of . The N-MOS single crystal TFT may include a single crystal silicon layer having the same crystal direction as the single crystal silicon layer of the P-MOS single crystal TFT and having a tensile stress greater than the single crystal silicon layer of the P-MOS single crystal TFT.

摘要翻译： 包括基板，形成在基板上的P-MOS单晶TFT的半导体器件和形成在P-MOS单晶TFT上的N-MOS单晶TFT。 P-MOS单晶TFT的源极区域和N-MOS单晶TFT的源极区域可以彼此连接。 P-MOS单晶TFT和N-MOS单晶TFT可以共用公共栅极。 此外，P-MOS单晶TFT可以包括具有（100）的晶面和<100>的晶体方向的单晶硅层。 N-MOS单晶TFT可以包括与P-MOS单晶TFT的单晶硅层相同的晶体方向的单晶硅层，其拉应力大于P-MOS的单晶硅层 单晶TFT。

公开(公告)号：US07772711B2

公开(公告)日：2010-08-10

申请号：US11430117

申请日：2006-05-09

申请人： Takashi Noguchi ,  Hans S. Cho ,  Wenxu Xianyu ,  Do-young Kim ,  Jang-yeong Kwon ,  Huaxiang Yin ,  Kyung-bae Park ,  Xiaoxin Zhang

发明人： Takashi Noguchi ,  Hans S. Cho ,  Wenxu Xianyu ,  Do-young Kim ,  Jang-yeong Kwon ,  Huaxiang Yin ,  Kyung-bae Park ,  Xiaoxin Zhang

IPC分类号： H01L27/11

CPC分类号： H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7842 ,  Y10S257/903

摘要： A semiconductor device including a substrate, a P-MOS single crystal TFT formed on the substrate, and an N-MOS single crystal TFT formed on the P-MOS single crystal TFT. The source region of the P-MOS single crystal TFT and the source region of the N-MOS single crystal TFT may be connected to each other. The P-MOS single crystal TFT and the N-MOS single crystal TFT may share a common gate. Also, the P-MOS single crystal TFT may include a single crystal silicon layer with a crystal plane of (100) and a crystal direction of . The N-MOS single crystal TFT may include a single crystal silicon layer having the same crystal direction as the single crystal silicon layer of the P-MOS single crystal TFT and having a tensile stress greater than the single crystal silicon layer of the P-MOS single crystal TFT.

摘要翻译： 包括基板，形成在基板上的P-MOS单晶TFT的半导体器件和形成在P-MOS单晶TFT上的N-MOS单晶TFT。 P-MOS单晶TFT的源极区域和N-MOS单晶TFT的源极区域可以彼此连接。 P-MOS单晶TFT和N-MOS单晶TFT可以共用公共栅极。 此外，P-MOS单晶TFT可以包括具有（100）的晶面并且晶体方向<100的单晶硅层。 N-MOS单晶TFT可以包括与P-MOS单晶TFT的单晶硅层相同的晶体方向的单晶硅层，其拉应力大于P-MOS的单晶硅层 单晶TFT。

公开(公告)号：US20050145843A1

公开(公告)日：2005-07-07

申请号：US11013398

申请日：2004-12-17

申请人： Huaxiang Yin ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-young Kim

发明人： Huaxiang Yin ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-young Kim

IPC分类号： H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786 ,  H01L29/04 ,  H01L21/00

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/7855

摘要： A thin film transistor and a method of manufacturing the same are provided. The thin film transistor includes a substrate; a buffer layer formed on the substrate; a source and a drain spaced apart from each other on the buffer layer; a channel layer formed on the buffer layer to connect the source and the drain with each other; and a gate formed on the buffer layer to be spaced apart from the source, the drain and the channel layer.

摘要翻译： 提供薄膜晶体管及其制造方法。 薄膜晶体管包括基板; 形成在所述基板上的缓冲层; 在缓冲层上彼此间隔开的源极和漏极; 形成在所述缓冲层上的沟道层，以将所述源极和所述漏极彼此连接; 以及形成在缓冲层上以与源极，漏极和沟道层间隔开的栅极。

公开(公告)号：US20060220034A1

公开(公告)日：2006-10-05

申请号：US11369947

申请日：2006-03-08

申请人： Huaxiang Yin ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-young Kim ,  Ji-sim Jung ,  Jang-yeon Kwon

发明人： Huaxiang Yin ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-young Kim ,  Ji-sim Jung ,  Jang-yeon Kwon

IPC分类号： H01L33/00

CPC分类号： H01L29/66757 ,  H01L29/4908

摘要： A thin film transistor and a method of manufacturing the thin film transistor. The thin film transistor may include a substrate, a buffer layer, a polysilicon layer, a gate insulating layer and/or a gate electrode, and a capping layer. The buffer layer may be formed on the substrate. The polysilicon layer may be formed on the buffer layer, and may include a first doped region, a second doped region, and a channel region. The gate insulating layer and a gate electrode may be sequentially stacked on the channel region of the polysilicon layer. The capping layer may be stacked on the gate electrode.

摘要翻译： 一种薄膜晶体管及其制造方法。 薄膜晶体管可以包括衬底，缓冲层，多晶硅层，栅极绝缘层和/或栅电极以及覆盖层。 缓冲层可以形成在衬底上。 多晶硅层可以形成在缓冲层上，并且可以包括第一掺杂区域，第二掺杂区域和沟道区域。 栅极绝缘层和栅电极可以顺序堆叠在多晶硅层的沟道区上。 覆盖层可以堆叠在栅电极上。

公开(公告)号：US07768010B2

公开(公告)日：2010-08-03

申请号：US12216701

申请日：2008-07-09

申请人： Do-young Kim ,  Takashi Noguchi

发明人： Do-young Kim ,  Takashi Noguchi

IPC分类号： H01L31/0376 ,  H01L31/20 ,  H01L21/00

CPC分类号： H01L27/124 ,  H01L29/42384

摘要： Provided are a poly crystalline silicon semiconductor device and a method of fabricating the same. Portions of a silicon layer except for gates are removed to reduce a parasitic capacitance caused from the silicon layer existing on gate bus lines. The silicon layer exists under the gates only, thus the parasitic capacitance is reduced and the deterioration and the delay of signals are prevented. Accordingly, the poly crystalline silicon semiconductor device, such as a thin film transistor, has excellent electric characteristics.

摘要翻译： 提供一种多晶硅半导体器件及其制造方法。 除去栅极以外的硅层的部分被去除以减少由存在于栅极总线上的硅层引起的寄生电容。 硅层仅存在于栅极之下，因此寄生电容减小，并且防止信号的劣化和延迟。 因此，诸如薄膜晶体管的多晶硅半导体器件具有优异的电特性。

公开(公告)号：US20050139919A1

公开(公告)日：2005-06-30

申请号：US10980838

申请日：2004-11-04

申请人： Kyung-bae Park ,  Takashi Noguchi ,  Se-young Cho ,  Do-young Kim ,  Jang-yeon Kwon

发明人： Kyung-bae Park ,  Takashi Noguchi ,  Se-young Cho ,  Do-young Kim ,  Jang-yeon Kwon

IPC分类号： H01L21/20 ,  H01L21/00 ,  H01L21/336 ,  H01L27/01 ,  H01L29/786

CPC分类号： H01L29/66757 ,  H01L29/78603 ,  H01L29/78606

摘要： In a method of forming a polysilicon film, a thin film transistor including a polysilicon film, and a method of manufacturing a thin film transistor including a polysilicon film, the thin film transistor includes a substrate, a first heat conduction film on the substrate, a second heat conduction film adjacent to the first heat conduction film, the second heat conduction film having a lower thermal conductivity than the first heat conduction film, a polysilicon film on the second heat conduction film and the first heat conduction film adjacent to the second heat conduction film, and a gate stack on the polysilicon film. The second heat conduction film may either be on the first heat conduction film or, alternatively, the first heat conduction film may be non-contiguous and the second heat conduction film may be interposed between portions of the non-contiguous first heat conduction film.

摘要翻译： 在形成多晶硅膜的方法中，包括多晶硅膜的薄膜晶体管和包括多晶硅膜的薄膜晶体管的制造方法，薄膜晶体管包括基板，基板上的第一导热膜， 与所述第一导热膜相邻的所述第二导热膜，所述第二导热膜的热导率低于所述第一导热膜，所述第二导热膜上的多晶硅膜和与所述第二导热膜相邻的所述第一导热膜 膜和多晶硅膜上的栅极堆叠。 第二导热膜可以在第一导热膜上，或者第一导热膜可以不连续，并且第二导热膜可以介于不连续的第一导热膜的部分之间。

公开(公告)号：US07923316B2

公开(公告)日：2011-04-12

申请号：US11808521

申请日：2007-06-11

申请人： Kyung-bae Park ,  Takashi Noguchi ,  Se-young Cho ,  Do-young Kim ,  Jang-yeon Kwon

发明人： Kyung-bae Park ,  Takashi Noguchi ,  Se-young Cho ,  Do-young Kim ,  Jang-yeon Kwon

IPC分类号： H01L21/00

CPC分类号： H01L29/66757 ,  H01L29/78603 ,  H01L29/78606

摘要： In a method of forming a polysilicon film, a thin film transistor including a polysilicon film, and a method of manufacturing a thin film transistor including a polysilicon film, the thin film transistor includes a substrate, a first heat conduction film on the substrate, a second heat conduction film adjacent to the first heat conduction film, the second heat conduction film having a lower thermal conductivity than the first heat conduction film, a polysilicon film on the second heat conduction film and the first heat conduction film adjacent to the second heat conduction film, and a gate stack on the polysilicon film. The second heat conduction film may either be on the first heat conduction film or, alternatively, the first heat conduction film may be non-contiguous and the second heat conduction film may be interposed between portions of the non-contiguous first heat conduction film.

摘要翻译： 在形成多晶硅膜的方法中，包括多晶硅膜的薄膜晶体管和包括多晶硅膜的薄膜晶体管的制造方法，薄膜晶体管包括基板，基板上的第一导热膜， 与所述第一导热膜相邻的所述第二导热膜，所述第二导热膜的热导率低于所述第一导热膜，所述第二导热膜上的多晶硅膜和与所述第二导热膜相邻的所述第一导热膜 膜和多晶硅膜上的栅极堆叠。 第二导热膜可以在第一导热膜上，或者第一导热膜可以不连续，并且第二导热膜可以介于不连续的第一导热膜的部分之间。

公开(公告)号：US07479667B2

公开(公告)日：2009-01-20

申请号：US11022756

申请日：2004-12-28

申请人： Jang-yeon Kwon ,  Takashi Noguchi ,  Young-soo Park ,  Do-young Kim

发明人： Jang-yeon Kwon ,  Takashi Noguchi ,  Young-soo Park ,  Do-young Kim

IPC分类号： H01L29/76 ,  H01L29/745

CPC分类号： H01L29/78696 ,  H01L21/02532 ,  H01L21/02686 ,  H01L21/2026 ,  H01L27/1285 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/1029 ,  H01L29/6675 ,  H01L29/78663 ,  H01L29/78672

摘要： Provided are a semiconductor device including an active area which is defined as high and low mobility areas and a thin film transistor having the semiconductor device. The mobility of the active area can be lowered to a level enough to satisfy the requirement of the semiconductor device. The lowering of the mobility of the active area can contribute to reducing mobility deviation between semiconductor devices. As a result, the quality of a flat panel display adopting a large-scale semiconductor device can be greatly improved.

摘要翻译： 提供了包括被定义为高和低迁移率区域的有源区域和具有半导体器件的薄膜晶体管的半导体器件。 有源面积的迁移率可以降低到足以满足半导体器件要求的水平。 有源区的迁移率的降低有助于减少半导体器件之间的迁移率偏差。 结果，可以大大提高采用大规模半导体器件的平板显示器的质量。

公开(公告)号：US07390706B2

公开(公告)日：2008-06-24

申请号：US11289312

申请日：2005-11-30

申请人： Hans S. Cho ,  Takashi Noguchi ,  Do-young Kim

发明人： Hans S. Cho ,  Takashi Noguchi ,  Do-young Kim

IPC分类号： H01L21/84

CPC分类号： H01L21/02675 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/2026 ,  H01L27/1281 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66772

摘要： A method of forming a high quality channel region of a TFT by forming a large size monocrystalline silicon thin film using a patterned metal mask and a grain boundary filtering region is provided. The method includes sequentially stacking a first buffer layer and an amorphous silicon layer on a substrate, forming a first silicon region in which crystallization begins, a second silicon region having a width smaller than a width of the first silicon region and located on a central portion of a side of the first silicon region, and a third silicon region having a width than greater the width of the second silicon region and contacting the second silicon region, forming a metal mask partly on the first silicon region, and crystallizing the amorphous silicon layer by cooling the amorphous silicon layer after melting the entire amorphous silicon layer except for a portion of the amorphous silicon layer under the metal mask by radiating laser beams to the patterned amorphous silicon layer.

摘要翻译： 提供了通过使用图案化金属掩模和晶界过滤区域形成大尺寸单晶硅薄膜来形成TFT的高质量沟道区域的方法。 该方法包括在基板上依次层叠第一缓冲层和非晶硅层，形成开始结晶的第一硅区域，第二硅区域的宽度小于第一硅区域的宽度并位于中心部分 并且第三硅区域的宽度大于第二硅区域的宽度并与第二硅区域接触，部分地在第一硅区域上形成金属掩模，并且使非晶硅层结晶 通过对图案化的非晶硅层照射激光束，在金属掩模下方的非晶硅层的一部分熔融了整个非晶硅层之后，冷却非晶硅层。