公开(公告)号：US20060118886A1

公开(公告)日：2006-06-08

申请号：US11338330

申请日：2006-01-23

申请人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hui-Min Mao

发明人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hui-Min Mao

IPC分类号： H01L29/772

CPC分类号： H01L21/76897 ,  H01L21/76829 ,  H01L21/76895

摘要： A method of forming a bit line contact via. The method includes providing a substrate having a transistor with a gate electrode, drain region, and source region, forming a conductive layer overlying the drain region, conformally forming an insulating barrier layer overlying the substrate, blanketly forming a dielectric layer overlying the insulating barrier layer, and forming a via through the dielectric layer and insulating barrier layer, exposing the conductive layer.

摘要翻译： 形成位线接触通孔的方法。 该方法包括提供具有晶体管的衬底，该晶体管具有栅极，漏极区和源极区，形成覆盖漏极区的导电层，保形地形成覆盖衬底的绝缘阻挡层，覆盖在绝缘阻挡层上的绝缘层 并且通过介电层和绝缘阻挡层形成通孔，暴露导电层。

公开(公告)号：US07195975B2

公开(公告)日：2007-03-27

申请号：US10714001

申请日：2003-11-14

申请人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hui-Min Mao

发明人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hui-Min Mao

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L21/76897 ,  H01L21/76829 ,  H01L21/76895

摘要： A method of forming a bit line contact via. The method includes providing a substrate having a transistor with a gate electrode, drain region, and source region, forming a conductive layer overlying the drain region, conformally forming an insulating barrier layer overlying the substrate, blanketly forming a dielectric layer overlying the insulating barrier layer, and forming a via through the dielectric layer and insulating barrier layer, exposing the conductive layer.

摘要翻译： 形成位线接触通孔的方法。 该方法包括提供具有晶体管的衬底，该晶体管具有栅极，漏极区和源极区，形成覆盖漏极区的导电层，保形地形成覆盖衬底的绝缘阻挡层，覆盖在绝缘阻挡层上的绝缘层 并且通过介电层和绝缘阻挡层形成通孔，暴露导电层。

公开(公告)号：US06977134B2

公开(公告)日：2005-12-20

申请号：US10452274

申请日：2003-06-02

申请人： Chung-Peng Hao ,  Hui-Min Mao ,  Yi-Nan Chen ,  Tzu-Ching Tsai

发明人： Chung-Peng Hao ,  Hui-Min Mao ,  Yi-Nan Chen ,  Tzu-Ching Tsai

IPC分类号： H01L21/336 ,  G03C5/00

CPC分类号： H01L29/66583

摘要： A manufacturing method for a MOSFET gate structure. The method comprises providing a substrate, sequentially depositing a pad layer and a dielectric layer thereon, defining a gate trench passing through the dielectric layer and the pad layer to expose a predetermined gate area of the substrate, sequentially forming a gate dielectric layer, a first conductive layer, a second conductive layer, and a cap layer on the exposed substrate in the gate trench to form a damascene gate structure, and removing the dielectric layer.

摘要翻译： 一种用于MOSFET栅极结构的制造方法。 该方法包括提供衬底，在其上依次沉积衬垫层和电介质层，限定通过介电层和焊盘层的栅极沟槽，以暴露衬底的预定栅极区域，顺序地形成栅极电介质层，第一 导电层，第二导电层和盖层，以形成镶嵌栅极结构，并去除介电层。

公开(公告)号：US06709975B2

公开(公告)日：2004-03-23

申请号：US10222349

申请日：2002-08-16

申请人： Hui Min Mao ,  Yi-Nan Chen ,  Tzu-Ching Tsai

发明人： Hui Min Mao ,  Yi-Nan Chen ,  Tzu-Ching Tsai

IPC分类号： H01L214763

CPC分类号： H01L21/76837 ,  H01L21/76885

摘要： A method of forming inter-metal dielectric (IMD). A substrate having a patterned metal layer thereon has at least one opening to expose the substrate. The opening has an aspect ratio of 3.5˜4.5. Next, the opening is filled with a first dielectric layer, and voids are formed in the upper portion of the first dielectric layer due to the high aspect ratio opening. Thereafter, the first dielectric layer is etched to leave the first dielectric layer with a predetermined height in the opening without voids. Finally, a second dielectric layer is formed on the first dielectric layer to completely fill the opening.

摘要翻译： 一种形成金属间电介质（IMD）的方法。 其上具有图案化金属层的衬底具有至少一个露出衬底的开口。 开口的长宽比为3.5〜4.5。 接下来，开口填充有第一电介质层，并且由于高纵横比开口，在第一电介质层的上部形成空隙。 此后，蚀刻第一电介质层以使第一介电层在开口中具有预定的高度而没有空隙。 最后，在第一电介质层上形成第二电介质层以完全填充开口。

公开(公告)号：US06706587B1

公开(公告)日：2004-03-16

申请号：US10406371

申请日：2003-04-03

申请人： Tzu-Ching Tsai ,  Hui Min Mao ,  Ying Huan Chuang

发明人： Tzu-Ching Tsai ,  Hui Min Mao ,  Ying Huan Chuang

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L28/84 ,  H01L29/66181

摘要： Method for forming buried plates. The method includes providing a substrate formed with a pad stacked layer on the surface, a bottle trench and a protective layer on the upper sidewalls of the bottle trench, forming a doped hemispherical silicon grain (HSG) layer on the protective layer and the sidewalls and bottom of the bottle trench, removing the hemispherical silicon grain layer on the protective layer without removing the hemispherical silicon grain layer from the lower sidewalls and bottom of the bottle trench, forming a covering layer on the protective layer, and subjecting the doped hemispherical silicon grain layer to drive-in annealing so that ions in the HSG layer diffuse out to the substrate, thereby forming a buried plate within the lower sidewalls of the bottle trench.

摘要翻译： 掩埋板成型方法 该方法包括提供在表面上形成有垫堆叠层的基底，瓶沟槽和瓶沟槽的上侧壁上的保护层，在保护层和侧壁上形成掺杂半球形硅晶粒（HSG）层，以及 在瓶子沟槽的底部，去除保护层上的半球形硅晶粒层，而不从瓶沟槽的下侧壁和底部移除半球状硅晶粒层，在保护层上形成覆盖层，并对掺杂的半球形硅颗粒 层以驱动退火，使得HSG层中的离子扩散到衬底，从而在瓶沟槽的下侧壁内形成掩埋板。

公开(公告)号：US06838866B2

公开(公告)日：2005-01-04

申请号：US10283699

申请日：2002-10-30

申请人： Tzu-Ching Tsai ,  Hui Min Mao

发明人： Tzu-Ching Tsai ,  Hui Min Mao

IPC分类号： H01L21/334 ,  H01L21/66 ,  H01L21/762 ,  H01L21/8242 ,  H01L23/544 ,  H01L27/108 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L21/76224 ,  H01L22/12 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1087 ,  H01L29/66181

摘要： A process for measuring depth of a source and drain of a MOS transistor. The MOS transistor is formed on a semiconductor substrate on which a trench capacitor is formed and a buried strap is formed between the MOS transistor and the trench capacitor. The process includes the following steps. First, resistances of the buried strap at a plurality of different depths are measured. Next, a curve correlating the resistances with the depths is established. Next, slopes of the resistance to the depth for the curve are obtained. Finally, a depth corresponding to a minimum resistance before the slope of the resistance to the depth reaches to zero is obtained.

摘要翻译： 用于测量MOS晶体管的源极和漏极的深度的过程。 MOS晶体管形成在其上形成有沟槽电容器的半导体衬底上，并且在MOS晶体管和沟槽电容器之间形成掩埋带。 该过程包括以下步骤。 首先，测量在多个不同深度处的掩埋带的电阻。 接下来，建立将电阻与深度相关联的曲线。 接下来，获得对曲线的深度的阻力的斜率。 最后，获得与深度电阻斜率之前的最小电阻对应的深度达到零的深度。

公开(公告)号：US06703311B2

公开(公告)日：2004-03-09

申请号：US10163240

申请日：2002-06-04

申请人： Tzu-Ching Tsai ,  Hui Min Mao ,  Ying Huan Chuang ,  Yu-Pi Lee

发明人： Tzu-Ching Tsai ,  Hui Min Mao ,  Ying Huan Chuang ,  Yu-Pi Lee

IPC分类号： H01L21302

CPC分类号： H01L27/10861 ,  G01R31/275 ,  H01L22/34

摘要： A method for estimating capacitance of deep trench capacitor in a substrate. After a photoresist layer used to define the region of the lower electrode is formed on an oxide layer doping with a conducting type dopant, the height difference of the photoresist layer between the memory cell array area and the supporting area is measured. The radicand of the height difference is directly proportional to a capacitance of a capacitor to-be-formed in the trenches.

摘要翻译： 一种用于估计衬底中的深沟槽电容器的电容的方法。 在用于限定下电极的区域的光致抗蚀剂层形成在掺杂有导电型掺杂剂的氧化物层上之后，测量存储单元阵列区域和支撑区域之间的光致抗蚀剂层的高度差。 高度差的根数与沟槽中要形成的电容器的电容成正比。

公开(公告)号：US07341952B2

公开(公告)日：2008-03-11

申请号：US11348626

申请日：2006-02-07

申请人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

发明人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

IPC分类号： H01L21/302

CPC分类号： H01L27/1087 ,  C03C15/00 ,  H01L21/0332 ,  H01L21/3081

摘要： A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.

摘要翻译： 一种用于蚀刻衬底中的深沟槽的方法。 形成覆盖在基板上的多层硬掩模结构，其包括第一硬掩模层和设置在其上的至少一个第二硬掩模层。 第一硬掩模层由第一硼硅酸盐玻璃（BSG）层和上覆的第一未掺杂硅玻璃（USG）层组成，第二硬质掩模层由第二BSG层和第二USG层组成。 形成覆盖多层硬掩模结构的多晶硅层，然后蚀刻以形成其中的开口。 连续蚀刻多层硬掩模结构和开口下方的底层基板，同时在衬底中形成深沟槽并去除多晶硅层。 去除多层硬掩模结构。

公开(公告)号：US06815356B2

公开(公告)日：2004-11-09

申请号：US10379445

申请日：2003-03-03

申请人： Tzu-Ching Tsai ,  Hsin-Jung Ho ,  Yi-Nan Chen

发明人： Tzu-Ching Tsai ,  Hsin-Jung Ho ,  Yi-Nan Chen

IPC分类号： H01L21311

CPC分类号： H01L21/76232 ,  H01L27/1087 ,  H01L29/66181

摘要： A method for forming a bottle trench in a substrate having a pad structure and a trench. First, a first insulating layer is formed in the trench, and a portion of the first insulating layer is removed to a certain depth of the trench. Next, a second insulating layer is formed in the trench, and portions of the second insulating layer on the pad structure and the sidewalls of the trench are removed. Next, an etching stop layer is formed in the trench, and a bottom portion of the etching stop layer is removed. Finally, the etching stop layer is used as a mask to remove the remaining second insulating layer and the first insulating layer.

摘要翻译： 一种在具有衬垫结构和沟槽的衬底中形成瓶沟槽的方法。 首先，在沟槽中形成第一绝缘层，并且将第一绝缘层的一部分去除到沟槽的一定深度。 接下来，在沟槽中形成第二绝缘层，并且去除衬垫结构上的第二绝缘层的部分和沟槽的侧壁。 接下来，在沟槽中形成蚀刻停止层，去除蚀刻停止层的底部。 最后，将蚀刻停止层用作掩模以去除剩余的第二绝缘层和第一绝缘层。

公开(公告)号：US20130102123A1

公开(公告)日：2013-04-25

申请号：US13276960

申请日：2011-10-19

申请人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/02

CPC分类号： H01L27/10867

摘要： A method for manufacturing a buried-strap includes: forming a trench capacitor structure in a semiconductor substrate, wherein the trench capacitor structure has a doped polysilicon layer and an isolation collar covered by the doped polysilicon layer, and a top surface of the doped polysilicon layer is lower than a top surface of the semiconductor substrate such that a first recess is formed; sequentially forming a first resist layer, a second resist layer and a third resist layer over the semiconductor substrate; sequentially patterning the third resist layer, the second resist layer and the first resist layer, forming a patterned tri-layer resist layer over the semiconductor substrate; partially removing a portion of the doped polysilicon layer exposed by the patterned tri-layer resist layer to form a second recess; removing the patterned tri-layer resist layer; and forming an insulating layer in the second recess and a portion of the first recess.

摘要翻译： 一种掩埋带的制造方法包括：在半导体衬底中形成沟槽电容器结构，其中沟槽电容器结构具有掺杂多晶硅层和由掺杂多晶硅层覆盖的隔离环，以及掺杂多晶硅层的顶表面 低于半导体衬底的顶表面，从而形成第一凹槽; 在半导体衬底上依次形成第一抗蚀剂层，第二抗蚀剂层和第三抗蚀剂层; 顺序地图案化第三抗蚀剂层，第二抗蚀剂层和第一抗蚀剂层，在半导体衬底上形成图案化的三层抗蚀剂层; 部分地去除由图案化的三层抗蚀剂层暴露的部分掺杂多晶硅层以形成第二凹槽; 去除图案化的三层抗蚀剂层; 以及在所述第二凹部中形成绝缘层和所述第一凹部的一部分。