Method of fabricating a GaN P-i-N diode using implantation
    5.
    发明授权
    Method of fabricating a GaN P-i-N diode using implantation 有权
    使用注入制造GaN P-i-N二极管的方法

    公开(公告)号:US08822311B2

    公开(公告)日:2014-09-02

    申请号:US13335329

    申请日:2011-12-22

    IPC分类号: H01L29/20 H01L29/24

    摘要: A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region.

    摘要翻译: III族氮化物半导体器件包括用于在III族氮化物半导体器件的正向偏置操作期间支持电流的有源区域。 有源区包括具有第一导电类型的第一III族氮化物外延材料和具有第二导电类型的第二III族氮化物外延材料。 III族氮化物半导体器件还包括物理地邻近有源区的边缘终端区,并且包括包含第一III族氮化物外延材料的一部分的注入区。 第一III族氮化物外延材料的注入区域相对于与注入区域相邻的第一III族氮化物外延材料的部分具有降低的导电性。

    GAN vertical superjunction device structures and fabrication methods
    6.
    发明授权
    GAN vertical superjunction device structures and fabrication methods 有权
    GAN垂直超结装置结构及制造方法

    公开(公告)号:US08785975B2

    公开(公告)日:2014-07-22

    申请号:US13529822

    申请日:2012-06-21

    摘要: A semiconductor device includes a III-nitride substrate of a first conductivity type, a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate, and a first III-nitride epitaxial structure coupled to a first portion of a surface of the first III-nitride epitaxial layer. The first III-nitride epitaxial structure has a sidewall. The semiconductor device further includes a second III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial structure, a second III-nitride epitaxial layer of the first conductivity type coupled to the sidewall of the second III-nitride epitaxial layer and a second portion of the surface of the first III-nitride epitaxial layer, and a third III-nitride epitaxial layer of a second conductivity type coupled to the second III-nitride epitaxial layer. The semiconductor device also includes one or more dielectric structures coupled to a surface of the third III-nitride epitaxial layer.

    摘要翻译: 半导体器件包括第一导电类型的III族氮化物衬底,耦合到III族氮化物衬底的第一导电类型的第一III族氮化物外延层和耦合到第一III族氮化物外延结构的第一部分 第一III族氮化物外延层的表面。 第一III族氮化物外延结构具有侧壁。 半导体器件还包括耦合到第一III族氮化物外延结构的第一导电类型的第二III族氮化物外延结构,第一导电类型的第二III族氮化物外延层耦合到第二III族氮化物外延的侧壁 层和第一III族氮化物外延层的表面的第二部分,以及耦合到第二III族氮化物外延层的第二导电类型的第三III族氮化物外延层。 半导体器件还包括耦合到第三III族氮化物外延层的表面的一个或多个电介质结构。

    GAN VERTICAL SUPERJUNCTION DEVICE STRUCTURES AND FABRICATION METHODS
    7.
    发明申请
    GAN VERTICAL SUPERJUNCTION DEVICE STRUCTURES AND FABRICATION METHODS 有权
    GAN垂直超导装置结构和制造方法

    公开(公告)号:US20130341677A1

    公开(公告)日:2013-12-26

    申请号:US13529822

    申请日:2012-06-21

    IPC分类号: H01L27/088 H01L21/8234

    摘要: A semiconductor device includes a III-nitride substrate of a first conductivity type, a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate, and a first III-nitride epitaxial structure coupled to a first portion of a surface of the first III-nitride epitaxial layer. The first III-nitride epitaxial structure has a sidewall. The semiconductor device further includes a second III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial structure, a second III-nitride epitaxial layer of the first conductivity type coupled to the sidewall of the second III-nitride epitaxial layer and a second portion of the surface of the first III-nitride epitaxial layer, and a third III-nitride epitaxial layer of a second conductivity type coupled to the second III-nitride epitaxial layer. The semiconductor device also includes one or more dielectric structures coupled to a surface of the third III-nitride epitaxial layer.

    摘要翻译: 半导体器件包括第一导电类型的III族氮化物衬底,耦合到III族氮化物衬底的第一导电类型的第一III族氮化物外延层和耦合到第一III族氮化物外延结构的第一部分 第一III族氮化物外延层的表面。 第一III族氮化物外延结构具有侧壁。 半导体器件还包括耦合到第一III族氮化物外延结构的第一导电类型的第二III族氮化物外延结构,第一导电类型的第二III族氮化物外延层耦合到第二III族氮化物外延的侧壁 层和第一III族氮化物外延层的表面的第二部分,以及耦合到第二III族氮化物外延层的第二导电类型的第三III族氮化物外延层。 半导体器件还包括耦合到第三III族氮化物外延层的表面的一个或多个电介质结构。

    Method and system for a GAN vertical JFET utilizing a regrown gate
    9.
    发明授权
    Method and system for a GAN vertical JFET utilizing a regrown gate 有权
    使用再生栅的GAN垂直JFET的方法和系统

    公开(公告)号:US09184305B2

    公开(公告)日:2015-11-10

    申请号:US13198655

    申请日:2011-08-04

    摘要: A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.

    摘要翻译: 垂直III族氮化物场效应晶体管包括:包含第一III族氮化物材料的漏极,与漏极电耦合的漏极接触点;以及漂移区域,包括耦合到漏极并邻近漏极设置的第二III族氮化物材料 垂直方向 场效应晶体管还包括沟道区,该沟道区包括耦合到漂移区的第三III族氮化物材料,至少部分围绕沟道区的栅极区和电耦合到栅极区的栅极接触。 场效应晶体管还包括耦合到沟道区的源极和电耦合到源极的源极接触。 沟道区域沿着垂直方向设置在漏极和源极之间,使得垂直III族氮化物场效应晶体管的工作期间的电流沿着垂直方向。