公开(公告)号：US20080079037A1

公开(公告)日：2008-04-03

申请号：US11538174

申请日：2006-10-03

申请人： Huilong Zhu ,  Ravikumar Ramachandran ,  Effendi Leobandung ,  Mahender Kumar ,  Wenjuan Zhu ,  Christine Norris

发明人： Huilong Zhu ,  Ravikumar Ramachandran ,  Effendi Leobandung ,  Mahender Kumar ,  Wenjuan Zhu ,  Christine Norris

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/78696 ,  H01L29/78648

摘要： A semiconductor structure includes a semiconductor layer that includes an inverted V shaped channel region that allows avoidance of a raised source/drain region within the semiconductor structure. In one embodiment, a generally conventional gate electrode is located over a planar surface of the semiconductor layer over the inverted V shaped channel region. In another embodiment, the foregoing generally conventional gate electrode is used in conjunction with an inverted V shaped gate electrode that is located within an inverted V shaped notch that comprises the inverted V shaped channel region.

摘要翻译： 半导体结构包括半导体层，其包括反向V形沟道区域，其允许避免半导体结构内的升高的源极/漏极区域。 在一个实施例中，通常常规的栅电极位于反向V形沟道区上的半导体层的平面表面上方。 在另一个实施例中，上述通常的常规栅极电极与位于包括反向V形沟道区域的倒V形凹口内的反向V形栅电极结合使用。

公开(公告)号：US07485510B2

公开(公告)日：2009-02-03

申请号：US11538174

申请日：2006-10-03

申请人： Huilong Zhu ,  Ravikumar Ramachandran ,  Effendi Leobandung ,  Mahender Kumar ,  Wenjuan Zhu ,  Christine Norris

发明人： Huilong Zhu ,  Ravikumar Ramachandran ,  Effendi Leobandung ,  Mahender Kumar ,  Wenjuan Zhu ,  Christine Norris

IPC分类号： H01L21/84

CPC分类号： H01L29/78696 ,  H01L29/78648

摘要： A semiconductor structure includes a semiconductor layer that includes an inverted V shaped channel region that allows avoidance of a raised source/drain region within the semiconductor structure. In one embodiment, a generally conventional gate electrode is located over a planar surface of the semiconductor layer over the inverted V shaped channel region. In another embodiment, the foregoing generally conventional gate electrode is used in conjunction with an inverted V shaped gate electrode that is located within an inverted V shaped notch that comprises the inverted V shaped channel region.

摘要翻译： 半导体结构包括半导体层，其包括反向V形沟道区域，其允许避免半导体结构内的升高的源极/漏极区域。 在一个实施例中，通常常规的栅电极位于反向V形沟道区上的半导体层的平面表面上方。 在另一个实施例中，上述通常的常规栅极电极与位于包括反向V形沟道区域的倒V形凹口内的反向V形栅电极结合使用。

公开(公告)号：US07528027B1

公开(公告)日：2009-05-05

申请号：US12054727

申请日：2008-03-25

申请人： Huilong Zhu ,  Mahender Kumar ,  Dan M. Mocuta ,  Ravikumar Ramachandran ,  Wenjuan Zhu

发明人： Huilong Zhu ,  Mahender Kumar ,  Dan M. Mocuta ,  Ravikumar Ramachandran ,  Wenjuan Zhu

IPC分类号： H01L21/336

CPC分类号： H01L29/78696 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/84 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66772

摘要： An SOI CMOS structure includes a v-shape trench in a pFet region. The v-shape trench has a surface in a (111) plane and extends into an SOI layer in the pFet region. A layer, such as a gate oxide or high-k material, is formed in the v-shape trench. Poly-Si is deposited on top of the layer.

摘要翻译： SOI CMOS结构包括pFet区域中的v形沟槽。 V形沟槽具有（111）面中的表面并延伸到pFet区域中的SOI层。 在V形沟槽中形成诸如栅极氧化物或高k材料的层。 多晶硅沉积在层的顶部。

公开(公告)号：US20090072400A1

公开(公告)日：2009-03-19

申请号：US11856839

申请日：2007-09-18

申请人： Huilong Zhu ,  James J. Heaps-Nelson ,  Mahender Kumar ,  Christine Norris ,  Ravikumar Ramachandran

发明人： Huilong Zhu ,  James J. Heaps-Nelson ,  Mahender Kumar ,  Christine Norris ,  Ravikumar Ramachandran

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L23/485 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76847 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming a contact in two or more portions and a contact so formed are disclosed. One method includes providing a device including a silicide region; and forming a contact to the silicide region by: first forming a lower contact portion to the silicide region through a first dielectric layer, and second forming an upper contact portion to the lower contact portion through a second dielectric layer over the first dielectric layer. A contact may include a first contact portion contacting a silicide region, the first contact portion having a width less than 100 nm; and a second contact portion coupled to the first contact portion from above, the second contact portion having a width greater than the width of the first contact portion.

摘要翻译： 公开了在两个或多个部分形成接触的方法和如此形成的接触。 一种方法包括提供包括硅化物区域的器件; 以及通过以下步骤形成与所述硅化物区的接触：首先通过第一介电层形成到所述硅化物区的下接触部分，以及通过所述第一电介质层上的第二电介质层，在所述下接触部分形成上接触部分。 接触可以包括接触硅化物区域的第一接触部分，第一接触部分具有小于100nm的宽度; 以及从上方联接到所述第一接触部分的第二接触部分，所述第二接触部分的宽度大于所述第一接触部分的宽度。

公开(公告)号：US07268049B2

公开(公告)日：2007-09-11

申请号：US10954838

申请日：2004-09-30

申请人： Huilong Zhu ,  Effendi Leobandung ,  Anda C. Mocuta ,  Dan M. Mocuta

发明人： Huilong Zhu ,  Effendi Leobandung ,  Anda C. Mocuta ,  Dan M. Mocuta

IPC分类号： H01L21/336

CPC分类号： H01L29/7842 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.

摘要翻译： 本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。 低扩散性层可以是Si 1-xy X z Z z，其中Z可以是碳（C），氙（Xe）， 锗（Ge），氪（Kr），氩（Ar），氮（N）或其组合。

公开(公告)号：US20050242340A1

公开(公告)日：2005-11-03

申请号：US11062993

申请日：2005-02-22

申请人： Dureseti Chidambarrao ,  Effendi Leobandung ,  Anda Mocuta ,  Haining Yang ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Effendi Leobandung ,  Anda Mocuta ,  Haining Yang ,  Huilong Zhu

IPC分类号： C30B25/18 ,  C30B29/06 ,  H01L21/20 ,  H01L21/285 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072

CPC分类号： H01L29/78696 ,  C30B25/18 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/28562 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7834 ,  H01L29/78687

摘要： A planar NFET on a strained silicon layer supported by a SiGe layer achieves reduced external resistance by removing SiGe material outside the transistor body and below the strained silicon layer and replacing the removed material with epitaxial silicon, thereby providing lower resistance for the transistor electrodes and permitting better control over Arsenic diffusion.

公开(公告)号：US20080001213A1

公开(公告)日：2008-01-03

申请号：US11427405

申请日：2006-06-29

申请人： Huilong Zhu ,  Byeong Y. Kim ,  Effendi Leobandung

发明人： Huilong Zhu ,  Byeong Y. Kim ,  Effendi Leobandung

IPC分类号： H01L29/76

CPC分类号： H01L21/823878 ,  H01L21/76264 ,  H01L21/823814 ,  H01L21/82385 ,  H01L29/78696

摘要： Reverse narrow width effects are provided consistent with reduced spacing between field effect transistors by an impurity or dopant implantation perpendicular to a semiconductor substrate through gaps formed by selective removal of a layer of material deposited to a selected thickness rather than implantation at an angle in accordance with a patterned resist resulting in superior accuracy, controllability and repeatability of the location of the implanted region and avoidance of implantation at undesired locations. A multi-layer structure having at least three component materials which can be removed selectively to each other is preferred for forming the gaps for confining the implantation preferably performed through a layer of one of the component materials which also functions as an etch stop.

摘要翻译： 提供反向窄宽度效应与场效应晶体管之间的间隔减小，通过垂直于半导体衬底的杂质或掺杂剂注入，通过选择性去除沉积到所选厚度的材料层而形成的间隙，而不是按照 图案化的抗蚀剂导致注入区域的位置的优良精度，可控性和重复性以及避免植入在不期望的位置。 具有至少可以选择性地彼此移除的三种组分材料的多层结构优选用于形成用于限制注入的间隙，优选通过也用作蚀刻停止层的一种组分材料的层进行。

公开(公告)号：US20060060925A1

公开(公告)日：2006-03-23

申请号：US10711416

申请日：2004-09-17

申请人： Bruce Doris ,  Oleg Gluschenkov ,  MeiKei Ieong ,  Effendi Leobandung ,  Huilong Zhu

发明人： Bruce Doris ,  Oleg Gluschenkov ,  MeiKei Ieong ,  Effendi Leobandung ,  Huilong Zhu

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/045 ,  H01L21/76275 ,  H01L21/76278 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7842

摘要： Semiconductor structure and method to simultaneously achieve optimal stress type and current flow for both nFET and pFET devices, and for gates orientated in one direction, are disclosed. One embodiment of the method includes bonding a first wafer having a first surface direction and a first surface orientation atop a second wafer having a different second surface orientation and a different second surface direction; forming an opening through the first wafer to the second wafer; and forming a region in the opening coplanar with a surface of the first wafer, wherein the region has the second surface orientation and the second surface direction. The semiconductor device structure includes at least two active regions having different surface directions, each active region including one of a plurality of nFETs and a plurality of pFETs, and wherein a gate electrode orientation is such that the nFETs and the pFETs are substantially parallel to each other.

摘要翻译： 公开了同时实现nFET和pFET器件以及朝向一个方向的栅极的最佳应力类型和电流流动的半导体结构和方法。 该方法的一个实施例包括将具有第一表面方向的第一晶片和具有不同的第二表面取向和不同的第二表面方向的第二晶片顶部的第一表面取向接合; 形成通过所述第一晶片的开口到所述第二晶片; 以及在所述开口中形成与所述第一晶片的表面共面的区域，其中所述区域具有第二表面取向和所述第二表面方向。 半导体器件结构包括具有不同表面方向的至少两个有源区，每个有源区包括多个nFET和多个pFET中的一个，并且其中栅电极取向使得nFET和pFET基本上平行于每个 其他。

公开(公告)号：US07723750B2

公开(公告)日：2010-05-25

申请号：US11774221

申请日：2007-07-06

申请人： Huilong Zhu ,  Effendi Leobandung ,  Anda C. Mocuta ,  Dan M. Mocuta

发明人： Huilong Zhu ,  Effendi Leobandung ,  Anda C. Mocuta ,  Dan M. Mocuta

IPC分类号： H01L29/737

CPC分类号： H01L29/7842 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.

摘要翻译： 本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。 低扩散性层可以是Si1-x-yGexZy，其中Z可以是碳（C），氙（Xe），锗（Ge），氪（Kr），氩（Ar），氮（N）或它们的组合。

公开(公告)号：US07354806B2

公开(公告)日：2008-04-08

申请号：US10711416

申请日：2004-09-17

申请人： Bruce B. Doris ,  Oleg Gluschenkov ,  MeiKei Ieong ,  Effendi Leobandung ,  Huilong Zhu

发明人： Bruce B. Doris ,  Oleg Gluschenkov ,  MeiKei Ieong ,  Effendi Leobandung ,  Huilong Zhu

IPC分类号： H01L21/00

CPC分类号： H01L29/045 ,  H01L21/76275 ,  H01L21/76278 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7842

摘要： Semiconductor structure and method to simultaneously achieve optimal stress type and current flow for both nFET and pFET devices, and for gates orientated in one direction, are disclosed. One embodiment of the method includes bonding a first wafer having a first surface direction and a first surface orientation atop a second wafer having a different second surface orientation and a different second surface direction; forming an opening through the first wafer to the second wafer; and forming a region in the opening coplanar with a surface of the first wafer, wherein the region has the second surface orientation and the second surface direction. The semiconductor device structure includes at least two active regions having different surface directions, each active region including one of a plurality of nFETs and a plurality of pFETs, and wherein a gate electrode orientation is such that the nFETs and the pFETs are substantially parallel to each other.

摘要翻译： 公开了同时实现nFET和pFET器件以及朝向一个方向的栅极的最佳应力类型和电流流动的半导体结构和方法。 该方法的一个实施例包括将具有第一表面方向的第一晶片和具有不同的第二表面取向和不同的第二表面方向的第二晶片顶部的第一表面取向接合; 形成通过所述第一晶片的开口到所述第二晶片; 以及在所述开口中形成与所述第一晶片的表面共面的区域，其中所述区域具有第二表面取向和所述第二表面方向。 半导体器件结构包括具有不同表面方向的至少两个有源区，每个有源区包括多个nFET和多个pFET中的一个，并且其中栅电极取向使得nFET和pFET基本上平行于每个 其他。