公开(公告)号：US20080079037A1

公开(公告)日：2008-04-03

申请号：US11538174

申请日：2006-10-03

申请人： Huilong Zhu ,  Ravikumar Ramachandran ,  Effendi Leobandung ,  Mahender Kumar ,  Wenjuan Zhu ,  Christine Norris

发明人： Huilong Zhu ,  Ravikumar Ramachandran ,  Effendi Leobandung ,  Mahender Kumar ,  Wenjuan Zhu ,  Christine Norris

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/78696 ,  H01L29/78648

摘要： A semiconductor structure includes a semiconductor layer that includes an inverted V shaped channel region that allows avoidance of a raised source/drain region within the semiconductor structure. In one embodiment, a generally conventional gate electrode is located over a planar surface of the semiconductor layer over the inverted V shaped channel region. In another embodiment, the foregoing generally conventional gate electrode is used in conjunction with an inverted V shaped gate electrode that is located within an inverted V shaped notch that comprises the inverted V shaped channel region.

摘要翻译： 半导体结构包括半导体层，其包括反向V形沟道区域，其允许避免半导体结构内的升高的源极/漏极区域。 在一个实施例中，通常常规的栅电极位于反向V形沟道区上的半导体层的平面表面上方。 在另一个实施例中，上述通常的常规栅极电极与位于包括反向V形沟道区域的倒V形凹口内的反向V形栅电极结合使用。

公开(公告)号：US07485510B2

公开(公告)日：2009-02-03

申请号：US11538174

申请日：2006-10-03

申请人： Huilong Zhu ,  Ravikumar Ramachandran ,  Effendi Leobandung ,  Mahender Kumar ,  Wenjuan Zhu ,  Christine Norris

发明人： Huilong Zhu ,  Ravikumar Ramachandran ,  Effendi Leobandung ,  Mahender Kumar ,  Wenjuan Zhu ,  Christine Norris

IPC分类号： H01L21/84

CPC分类号： H01L29/78696 ,  H01L29/78648

摘要： A semiconductor structure includes a semiconductor layer that includes an inverted V shaped channel region that allows avoidance of a raised source/drain region within the semiconductor structure. In one embodiment, a generally conventional gate electrode is located over a planar surface of the semiconductor layer over the inverted V shaped channel region. In another embodiment, the foregoing generally conventional gate electrode is used in conjunction with an inverted V shaped gate electrode that is located within an inverted V shaped notch that comprises the inverted V shaped channel region.

摘要翻译： 半导体结构包括半导体层，其包括反向V形沟道区域，其允许避免半导体结构内的升高的源极/漏极区域。 在一个实施例中，通常常规的栅电极位于反向V形沟道区上的半导体层的平面表面上方。 在另一个实施例中，上述通常的常规栅极电极与位于包括反向V形沟道区域的倒V形凹口内的反向V形栅电极结合使用。

公开(公告)号：US07528027B1

公开(公告)日：2009-05-05

申请号：US12054727

申请日：2008-03-25

申请人： Huilong Zhu ,  Mahender Kumar ,  Dan M. Mocuta ,  Ravikumar Ramachandran ,  Wenjuan Zhu

发明人： Huilong Zhu ,  Mahender Kumar ,  Dan M. Mocuta ,  Ravikumar Ramachandran ,  Wenjuan Zhu

IPC分类号： H01L21/336

CPC分类号： H01L29/78696 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/84 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66772

摘要： An SOI CMOS structure includes a v-shape trench in a pFet region. The v-shape trench has a surface in a (111) plane and extends into an SOI layer in the pFet region. A layer, such as a gate oxide or high-k material, is formed in the v-shape trench. Poly-Si is deposited on top of the layer.

摘要翻译： SOI CMOS结构包括pFet区域中的v形沟槽。 V形沟槽具有（111）面中的表面并延伸到pFet区域中的SOI层。 在V形沟槽中形成诸如栅极氧化物或高k材料的层。 多晶硅沉积在层的顶部。

公开(公告)号：US20090072400A1

公开(公告)日：2009-03-19

申请号：US11856839

申请日：2007-09-18

申请人： Huilong Zhu ,  James J. Heaps-Nelson ,  Mahender Kumar ,  Christine Norris ,  Ravikumar Ramachandran

发明人： Huilong Zhu ,  James J. Heaps-Nelson ,  Mahender Kumar ,  Christine Norris ,  Ravikumar Ramachandran

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L23/485 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76847 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming a contact in two or more portions and a contact so formed are disclosed. One method includes providing a device including a silicide region; and forming a contact to the silicide region by: first forming a lower contact portion to the silicide region through a first dielectric layer, and second forming an upper contact portion to the lower contact portion through a second dielectric layer over the first dielectric layer. A contact may include a first contact portion contacting a silicide region, the first contact portion having a width less than 100 nm; and a second contact portion coupled to the first contact portion from above, the second contact portion having a width greater than the width of the first contact portion.

摘要翻译： 公开了在两个或多个部分形成接触的方法和如此形成的接触。 一种方法包括提供包括硅化物区域的器件; 以及通过以下步骤形成与所述硅化物区的接触：首先通过第一介电层形成到所述硅化物区的下接触部分，以及通过所述第一电介质层上的第二电介质层，在所述下接触部分形成上接触部分。 接触可以包括接触硅化物区域的第一接触部分，第一接触部分具有小于100nm的宽度; 以及从上方联接到所述第一接触部分的第二接触部分，所述第二接触部分的宽度大于所述第一接触部分的宽度。

公开(公告)号：US20130330899A1

公开(公告)日：2013-12-12

申请号：US13527063

申请日：2012-06-19

申请人： Huiming Bu ,  Ming Cai ,  Kevin K. Chan ,  Dechao Guo ,  Ravikumar Ramachandran ,  Liyang Song ,  Chun-Chen Yeh

发明人： Huiming Bu ,  Ming Cai ,  Kevin K. Chan ,  Dechao Guo ,  Ravikumar Ramachandran ,  Liyang Song ,  Chun-Chen Yeh

IPC分类号： H01L21/336 ,  H01L21/04

CPC分类号： H01L29/78 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/665 ,  H01L29/66628

摘要： A method of forming gate stack structure for a transistor device includes forming a gate dielectric layer over a substrate; forming a first silicon gate layer over the gate dielectric layer; forming a dopant-rich monolayer over the first silicon gate layer; and forming a second silicon gate layer over the dopant-rich monolayer, wherein the dopant-rich monolayer prevents silicidation of the first silicon gate layer during silicidation of the second silicon gate layer.

摘要翻译： 一种形成用于晶体管器件的栅叠层结构的方法包括在衬底上形成栅介电层; 在所述栅极介电层上形成第一硅栅极层; 在所述第一硅栅极层上形成富含掺杂剂的单层; 以及在所述富掺杂剂单层上形成第二硅栅极层，其中所述富掺杂剂层在所述第二硅栅极层的硅化期间防止所述第一硅栅极层的硅化。

公开(公告)号：US20120175711A1

公开(公告)日：2012-07-12

申请号：US12987221

申请日：2011-01-10

申请人： Ravikumar Ramachandran ,  Ramachandra Divakaruni ,  Ying Li

发明人： Ravikumar Ramachandran ,  Ramachandra Divakaruni ,  Ying Li

IPC分类号： H01L29/772 ,  H01L21/283

CPC分类号： H01L29/401 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/49 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/6656

摘要： A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located on a surface of the semiconductor substrate. Each gate stack includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks. Methods of forming the semiconductor structure using a replacement gate and a non-replacement gate scheme are also disclosed.

摘要翻译： 提供一种半导体结构，其包括具有位于半导体衬底的表面上的多个栅极叠层的半导体衬底。 每个栅极堆叠包括从底部到顶部的高k栅极电介质层，功函数金属层和导电金属。 间隔件位于每个栅极堆叠的侧壁上，并且自对准电介质衬垫存在于每个间隔件的上表面上。 每个自对准电介质衬垫的底表面存在于半导体金属合金的上表面上。 接触金属位于相邻的栅极堆叠之间，并通过自对准电介质衬垫与每个栅极堆叠分离。 该结构还包括另一个接触金属，其具有位于接触金属的上表面上且与触头金属的上表面直接接触的部分，以及位于与其中一个栅极叠层的导电金属直接接触的另一部分。 还公开了使用替换栅极和非替代栅极方案形成半导体结构的方法。

公开(公告)号：US08193099B1

公开(公告)日：2012-06-05

申请号：US13049933

申请日：2011-03-17

申请人： Mukesh V. Khare ,  Renee T. Mo ,  Ravikumar Ramachandran ,  Richard S. Wise ,  Hongwen Yan

发明人： Mukesh V. Khare ,  Renee T. Mo ,  Ravikumar Ramachandran ,  Richard S. Wise ,  Hongwen Yan

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/32136 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823828 ,  H01L21/823878

摘要： A method of forming a semiconductor device includes forming a transistor gate stack over a substrate having an active area and a shallow trench isolation (STI) region. First sidewall spacers are formed on the transistor gate stack, and an isotropic etch process is applied to isotropically remove an excess portion of a metal layer included within the transistor gate stack, the excess portion left unprotected by the first sidewall spacers. Second sidewall spacers are formed on the transistor gate stack, the second sidewall spacers completely encapsulating the metal layer of the transistor gate stack.

摘要翻译： 形成半导体器件的方法包括在具有有源区和浅沟槽隔离（STI）区的衬底上形成晶体管栅叠。 第一侧壁间隔物形成在晶体管栅极堆叠上，并且各向同性蚀刻工艺被应用于各向同性地去除包括在晶体管栅极叠层内的金属层的过剩部分，剩余部分未被第一侧壁间隔物保护。 第二侧壁间隔物形成在晶体管栅极叠层上，第二侧壁间隔物完全封装晶体管栅极叠层的金属层。

公开(公告)号：US20100187610A1

公开(公告)日：2010-07-29

申请号：US12359520

申请日：2009-01-26

申请人： Unoh Kwon ,  Siddarth A. Krishnan ,  Takashi Ando ,  Michael P. Chudzik ,  Martin M. Frank ,  William K. Henson ,  Rashmi Jha ,  Yue Liang ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Keith Kwong Hon Wong

发明人： Unoh Kwon ,  Siddarth A. Krishnan ,  Takashi Ando ,  Michael P. Chudzik ,  Martin M. Frank ,  William K. Henson ,  Rashmi Jha ,  Yue Liang ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Keith Kwong Hon Wong

IPC分类号： H01L29/78 ,  H01L21/3205

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/517

摘要： A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO2 and alpha-silicon layers or a dBARC layer.

摘要翻译： 半导体器件包括：半导体衬底; 形成在衬底上的PFET，PFET包括设置在衬底上的SiGe层，设置在SiGe层上的高K电介质层，设置在高k电介质层上的第一金属层，设置在第一中间层上的第一中间层 第一金属层，设置在第一中间层上的第二金属层，设置在第二金属层上的第二中间层和设置在第二中间层上的第三金属层; 形成在衬底上的NFET，NFET包括高k电介质层，高k电介质层设置在衬底上，第二中间层，第二中间层设置在高k电介质层上，并且 第三金属层，第三金属层设置在第二中间层上。 或者，省略第一金属层。 制造该器件的方法包括提供SiO 2和α-硅层或dBARC层。

公开(公告)号：US07670901B2

公开(公告)日：2010-03-02

申请号：US12033984

申请日：2008-02-20

申请人： Oh-Jung Kwon ,  Kenneth T. Settlemyer, Jr. ,  Ravikumar Ramachandran ,  Min-Soo Kim

发明人： Oh-Jung Kwon ,  Kenneth T. Settlemyer, Jr. ,  Ravikumar Ramachandran ,  Min-Soo Kim

IPC分类号： H01L21/762

CPC分类号： H01L27/1087 ,  H01L29/66181

摘要： A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent to the bottom of the trench; forming an oxidized layer of the substrate in the bottom region of the trench; and removing the oxidized layer of the substrate from the bottom region of the trench, a cross-sectional area of the lower region of the trench greater than a cross-sectional area of the upper region of the trench.

摘要翻译： 制造瓶沟槽和瓶沟电容器的方法。 该方法包括：提供衬底; 在所述衬底中形成沟槽，所述沟槽具有侧壁和底部，所述沟槽具有与所述衬底的顶表面相邻的上部区域和与所述沟槽的底部相邻的下部区域; 在沟槽的底部区域形成衬底的氧化层; 并且从沟槽的底部区域去除衬底的氧化层，沟槽的下部区域的横截面面积大于沟槽的上部区域的横截面面积。

公开(公告)号：US07498271B1

公开(公告)日：2009-03-03

申请号：US12145035

申请日：2008-06-24

申请人： Ricardo A. Donaton ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Xi Li ,  Renee T. Mo ,  Naim Moumen ,  Wesley C. Natzle ,  Ravikumar Ramachandran ,  Richard S. Wise

发明人： Ricardo A. Donaton ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Xi Li ,  Renee T. Mo ,  Naim Moumen ,  Wesley C. Natzle ,  Ravikumar Ramachandran ,  Richard S. Wise

IPC分类号： H01L21/31

CPC分类号： H01L21/31138 ,  H01L21/28202 ,  H01L21/31155 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： The present invention, in one embodiment, provides a method of forming a gate structure including providing a substrate including a semiconducting device region, a high-k dielectric material present atop the semiconducting device region, and a metal gate conductor atop the high-k dielectric material, applying a photoresist layer atop the metal gate conductor; patterning the photoresist layer to provide an etch mask overlying a portion of the metal gate conductor corresponding to a gate stack; etching the metal gate conductor and the high-k dielectric material selective to the etch mask; and removing the etch mask with a substantially oxygen free nitrogen based plasma.

摘要翻译： 本发明在一个实施例中提供了一种形成栅极结构的方法，该栅极结构包括提供包括半导体器件区域的衬底，在半导体器件区域顶部存在的高k电介质材料以及高k电介质顶部的金属栅极导体 材料，在金属栅极导体顶上施加光致抗蚀剂层; 图案化光致抗蚀剂层以提供覆盖对应于栅极堆叠的金属栅极导体的一部分的蚀刻掩模; 蚀刻对蚀刻掩模有选择性的金属栅极导体和高k电介质材料; 并用基本上不含氧的氮气等离子体去除蚀刻掩模。