公开(公告)号：US20090008705A1

公开(公告)日：2009-01-08

申请号：US11773607

申请日：2007-07-05

申请人： Huilong Zhu ,  Thomas W. Dyer ,  Jack A. Mandelman ,  Werner Rausch

发明人： Huilong Zhu ,  Thomas W. Dyer ,  Jack A. Mandelman ,  Werner Rausch

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7842 ,  H01L29/66795 ,  H01L29/785

摘要： A silicon containing fin is formed on a semiconductor substrate. A silicon oxide layer is formed around the bottom of the silicon containing fin. A gate dielectric is formed on the silicon containing fin followed by formation of a gate electrode. While protecting the portion of the semiconductor fin around the channel, a bottom portion of the silicon containing semiconductor fin is etched by a isotropic etch leaving a body strap between the channel of a finFET on the silicon containing fin and an underlying semiconductor layer underneath the silicon oxide layer. The fin may comprise a stack of inhomogeneous layers in which a bottom layer is etched selectively to a top semiconductor layer. Alternatively, the fin may comprise a homogeneous semiconductor material and the silicon containing fin may be protected by dielectric films on the sidewalls and top surfaces of the silicon containing fin.

摘要翻译： 在半导体衬底上形成含硅翅片。 在含硅翅片的底部周围形成氧化硅层。 在含硅鳍上形成栅电介质，形成栅电极。 在保护半导体翅片周围的通道的部分的同时，通过各向同性的蚀刻蚀刻含硅半导体鳍片的底部部分，从而在含硅鳍片上的finFET的通道和硅下方的下面的半导体层之间留下体带 氧化层。 翅片可以包括不均匀层的堆叠，其中底层被选择性地蚀刻到顶部半导体层。 或者，翅片可以包括均匀的半导体材料，并且含硅翅片可以由含硅翅片的侧壁和顶表面上的电介质膜保护。

公开(公告)号：US07485520B2

公开(公告)日：2009-02-03

申请号：US11773607

申请日：2007-07-05

申请人： Huilong Zhu ,  Thomas W. Dyer ,  Jack A. Mandelman ,  Werner Rausch

发明人： Huilong Zhu ,  Thomas W. Dyer ,  Jack A. Mandelman ,  Werner Rausch

IPC分类号： H01L21/336

CPC分类号： H01L29/7842 ,  H01L29/66795 ,  H01L29/785

摘要： A silicon containing fin is formed on a semiconductor substrate. A silicon oxide layer is formed around the bottom of the silicon containing fin. A gate dielectric is formed on the silicon containing fin followed by formation of a gate electrode. While protecting the portion of the semiconductor fin around the channel, a bottom portion of the silicon containing semiconductor fin is etched by a isotropic etch leaving a body strap between the channel of a finFET on the silicon containing fin and an underlying semiconductor layer underneath the silicon oxide layer. The fin may comprise a stack of inhomogeneous layers in which a bottom layer is etched selectively to a top semiconductor layer. Alternatively, the fin may comprise a homogeneous semiconductor material and the silicon containing fin may be protected by dielectric films on the sidewalls and top surfaces of the silicon containing fin.

摘要翻译： 在半导体衬底上形成含硅翅片。 在含硅翅片的底部周围形成氧化硅层。 在含硅鳍上形成栅电介质，形成栅电极。 在保护半导体翅片周围的通道的部分的同时，通过各向同性的蚀刻蚀刻含硅半导体鳍片的底部部分，从而在含硅鳍片上的finFET的通道和硅下方的下面的半导体层之间留下体带 氧化层。 翅片可以包括不均匀层的堆叠，其中底层被选择性地蚀刻到顶部半导体层。 或者，翅片可以包括均匀的半导体材料，并且含硅翅片可以由含硅翅片的侧壁和顶表面上的电介质膜保护。

公开(公告)号：US07981751B2

公开(公告)日：2011-07-19

申请号：US12566190

申请日：2009-09-24

申请人： Huilong Zhu ,  Werner Rausch

发明人： Huilong Zhu ,  Werner Rausch

IPC分类号： H01L21/336

CPC分类号： H01L21/28061 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845

摘要： A semiconductor structure including at least one transistor is provided which has a stressed channel region that is a result of having a stressed layer present atop a gate conductor that includes a stack comprising a bottom polysilicon (polySi) layer and a top metal semiconductor alloy (i.e., metal silicide) layer. The stressed layer is self-aligned to the gate conductor. The inventive structure also has a reduced external parasitic S/D resistance as a result of having a metallic contact located atop source/drain regions that include a surface region comprised of a metal semiconductor alloy. The metallic contact is self-aligned to the gate conductor.

摘要翻译： 提供了包括至少一个晶体管的半导体结构，其具有应力沟道区，其是在栅极导体顶部具有应力层的结果，该应力层包括包括底部多晶硅（polySi）层和顶部金属半导体合金（即， ，金属硅化物）层。 应力层与栅极导体自对准。 由于在包括由金属半导体合金构成的表面区域的源极/漏极区域之上具有金属接触的结果，本发明的结构还具有减小的外部寄生S / D电阻。 金属触点与栅极导体自对准。

公开(公告)号：US07615831B2

公开(公告)日：2009-11-10

申请号：US11925168

申请日：2007-10-26

申请人： Huilong Zhu ,  Werner Rausch

发明人： Huilong Zhu ,  Werner Rausch

IPC分类号： H01L31/119

CPC分类号： H01L21/28061 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845

摘要： A semiconductor structure including at least one transistor is provided which has a stressed channel region that is a result of having a stressed layer present atop a gate conductor that includes a stack comprising a bottom polysilicon (polySi) layer and a top metal semiconductor alloy (i.e., metal silicide) layer. The stressed layer is self-aligned to the gate conductor. The inventive structure also has a reduced external parasitic S/D resistance as a result of having a metallic contact located atop source/drain regions that include a surface region comprised of a metal semiconductor alloy. The metallic contact is self-aligned to the gate conductor.

摘要翻译： 提供了包括至少一个晶体管的半导体结构，其具有应力沟道区，其是在栅极导体顶部具有应力层的结果，所述应力层包括包括底部多晶硅（polySi）层和顶部金属半导体合金（即， ，金属硅化物）层。 应力层与栅极导体自对准。 由于在包括由金属半导体合金构成的表面区域的源极/漏极区域之上具有金属接触的结果，本发明的结构还具有减小的外部寄生S / D电阻。 金属触点与栅极导体自对准。

公开(公告)号：US20090108378A1

公开(公告)日：2009-04-30

申请号：US11925168

申请日：2007-10-26

申请人： Huilong Zhu ,  Werner Rausch

发明人： Huilong Zhu ,  Werner Rausch

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L21/28061 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845

摘要： A semiconductor structure including at least one transistor is provided which has a stressed channel region that is a result of having a stressed layer present atop a gate conductor that includes a stack comprising a bottom polysilicon (polySi) layer and a top metal semiconductor alloy (i.e., metal silicide) layer. The stressed layer is self-aligned to the gate conductor. The inventive structure also has a reduced external parasitic S/D resistance as a result of having a metallic contact located atop source/drain regions that include a surface region comprised of a metal semiconductor alloy. The metallic contact is self-aligned to the gate conductor.

摘要翻译： 提供了包括至少一个晶体管的半导体结构，其具有应力沟道区，其是在栅极导体顶部具有应力层的结果，该应力层包括包括底部多晶硅（polySi）层和顶部金属半导体合金（即， ，金属硅化物）层。 应力层与栅极导体自对准。 由于在包括由金属半导体合金构成的表面区域的源极/漏极区域之上具有金属接触的结果，本发明的结构还具有减小的外部寄生S / D电阻。 金属触点与栅极导体自对准。

公开(公告)号：US20100035400A1

公开(公告)日：2010-02-11

申请号：US12566190

申请日：2009-09-24

申请人： Huilong Zhu ,  Werner Rausch

发明人： Huilong Zhu ,  Werner Rausch

IPC分类号： H01L21/336

CPC分类号： H01L21/28061 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845

摘要： A semiconductor structure including at least one transistor is provided which has a stressed channel region that is a result of having a stressed layer present atop a gate conductor that includes a stack comprising a bottom polysilicon (polySi) layer and a top metal semiconductor alloy (i.e., metal silicide) layer. The stressed layer is self-aligned to the gate conductor. The inventive structure also has a reduced external parasitic S/D resistance as a result of having a metallic contact located atop source/drain regions that include a surface region comprised of a metal semiconductor alloy. The metallic contact is self-aligned to the gate conductor.

摘要翻译： 提供了包括至少一个晶体管的半导体结构，其具有应力沟道区，其是在栅极导体顶部具有应力层的结果，该应力层包括包括底部多晶硅（polySi）层和顶部金属半导体合金（即， ，金属硅化物）层。 应力层与栅极导体自对准。 由于在包括由金属半导体合金构成的表面区域的源极/漏极区域之上具有金属接触的结果，本发明的结构还具有减小的外部寄生S / D电阻。 金属触点与栅极导体自对准。

公开(公告)号：US20050090066A1

公开(公告)日：2005-04-28

申请号：US10605726

申请日：2003-10-22

申请人： Huilong Zhu ,  Bruce Doris ,  Werner Rausch ,  Ying Zhang

发明人： Huilong Zhu ,  Bruce Doris ,  Werner Rausch ,  Ying Zhang

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/00 ,  H01L21/8234

CPC分类号： H01L29/66621 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78687

摘要： An RSD FET device with a recessed channel is formed with a raised silicon S/D and a gate electrode structure on an SOI structure by the steps as follows. Form a SiGe layer over the silicon layer and a RSD layer over the SiGe. Etch through the RSD layer and the SiGe to form a gate electrode space reaching down the silicon layer. Form a pair of RSD regions separated by the gate electrode space. Line the walls of the gate electrode space with an internal etch stop layer and an inner sidewall spacers. Form a gate electrode inside the inner sidewall spacers on the silicon layer. Form external sidewall spacers adjacent to the gate electrode between the RSD regions next to the inner sidewall spacers, and dope the RSD regions, whereby a recessed channel is formed in the SOI silicon layer between the raised source/drain regions above the SiGe layer.

摘要翻译： 具有凹陷沟道的RSD FET器件通过以下步骤在SOI结构上形成有凸起的硅S / D和栅电极结构。 在硅层上形成SiGe层，并在SiGe上形成RSD层。 通过RSD层和SiGe蚀刻以形成向下延伸到硅层的栅电极空间。 形成一对被栅电极间隔开的RSD区域。 用内部蚀刻停止层和内侧壁间隔物来排列栅电极空间的壁。 在硅层上的内侧墙壁内形成栅电极。 在靠近内侧壁间隔区的RSD区域之间形成与栅电极相邻的外侧壁间隔物，并掺杂RSD区域，由此在SiGe层上方的凸起的源极/漏极区域之间的SOI硅层中形成凹陷沟道。

公开(公告)号：US07361959B2

公开(公告)日：2008-04-22

申请号：US11164515

申请日：2005-11-28

申请人： Christopher D. Sheraw ,  Alyssa C. Bonnoit ,  K. Paul Muller ,  Werner Rausch

发明人： Christopher D. Sheraw ,  Alyssa C. Bonnoit ,  K. Paul Muller ,  Werner Rausch

IPC分类号： H01L29/76

CPC分类号： H01L27/0629 ,  H01L21/26506 ,  H01L28/20 ,  H01L28/40 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits, as well as methods for forming such CMOS circuits. More specifically, the present invention relates to CMOS circuits that contain passive elements, such as buried resistors, capacitors, diodes, inductors, attenuators, power dividers, and antennas, etc., which are characterized by an end contact resistance of less than 90 ohm-microns. Such a low end resistance can be achieved either by reducing the spacer widths of the passive elements to a range of from about 10 nm to about 30 nm, or by masking the passive elements during a pre-amorphization implantation step, so that the passive elements are essentially free of pre-amorphization implants.

摘要翻译： 本发明涉及互补金属氧化物半导体（CMOS）电路，以及用于形成这种CMOS电路的方法。 更具体地说，本发明涉及包含诸如埋地电阻器，电容器，二极管，电感器，衰减器，功率分配器和天线等无源元件的CMOS电路，其特征在于端接触电阻小于90欧姆 微量元素 这样的低端电阻可以通过将无源元件的间隔物宽度减小到约10nm至约30nm的范围，或通过在预非晶化注入步骤期间掩蔽无源元件来实现，使得无源元件 基本上没有前非晶化植入物。

公开(公告)号：US20060076627A1

公开(公告)日：2006-04-13

申请号：US10711899

申请日：2004-10-12

申请人： Huajie Chen ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Werner Rausch

发明人： Huajie Chen ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Werner Rausch

IPC分类号： H01L29/94

CPC分类号： H01L21/26533 ,  H01L21/02238 ,  H01L21/26513 ,  H01L21/31654 ,  H01L21/31675 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/66636

摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

摘要翻译： 形成场效应晶体管的方法产生更浅和更尖的结，同时在与当前制造技术一致的工艺中最大化掺杂剂活化。 更具体地，本发明增加了硅衬底的顶表面的氧含量。 优选在增加硅衬底的顶表面的氧含量之前清洁硅衬底的顶表面。 硅衬底的顶表面的氧含量高于硅衬底的其它部分，但低于防止外延生长的量。 这允许本发明在硅​​衬底的顶表面上外延生长硅层。 此外，增加的氧含量基本上限制外延硅层内的掺杂剂移动到硅衬底中。

公开(公告)号：US20060065914A1

公开(公告)日：2006-03-30

申请号：US10711637

申请日：2004-09-29

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner Rausch ,  Tsutomu Sato ,  Henry Utomo

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner Rausch ,  Tsutomu Sato ,  Henry Utomo

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28079 ,  H01L21/7624 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.