公开(公告)号：US20060065914A1

公开(公告)日：2006-03-30

申请号：US10711637

申请日：2004-09-29

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner Rausch ,  Tsutomu Sato ,  Henry Utomo

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner Rausch ,  Tsutomu Sato ,  Henry Utomo

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28079 ,  H01L21/7624 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

公开(公告)号：US20060292779A1

公开(公告)日：2006-12-28

申请号：US11463777

申请日：2006-08-10

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner Rausch ,  Tsutomu Sato ,  Henry Utomo

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner Rausch ,  Tsutomu Sato ,  Henry Utomo

IPC分类号： H01L21/8234

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28079 ,  H01L21/7624 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

摘要翻译： 提供场效应晶体管（“FET”），其包括覆盖衬底的单晶半导体区域的栅极堆叠，设置在所述栅极堆叠的侧壁上的一对第一间隔区，以及基本上由单个 晶体半导体合金，其设置在栅叠层的相对侧上。 每个半导体合金区域与栅极叠层隔开第一距离。 FET的源极区域和漏极区域至少部分地设置在半导体合金区域的相应半导体合金区域中，使得源极区域和漏极区域之间的距离与栅极叠层间隔开第二距离， 第一间隔物，第二距离与第一距离不同。

公开(公告)号：US20060151837A1

公开(公告)日：2006-07-13

申请号：US10905598

申请日：2005-01-12

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Siddhartha Panda ,  Sang-Hyun Oh ,  Henry Utomo ,  Werner Rausch

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Siddhartha Panda ,  Sang-Hyun Oh ,  Henry Utomo ,  Werner Rausch

IPC分类号： H01L29/94

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

摘要： Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained epitaxial silicon germanium, wherein the strained silicon germanium comprises of two layers, with a top layer that is closer to the gate stack than the bottom layer. The strained silicon germanium is in-situ doped and creates longitudinal stress on the channel region.

摘要翻译： 公开了一种集成电路结构以及在衬底上具有衬底和P型和N型晶体管的结构的方法。 N型晶体管延伸和源极/漏极区域包括注入到衬底中的掺杂剂。 P型晶体管延伸和源极/漏极区域部分地包括应变外延硅锗，其中应变硅锗包括两层，顶层比底层更靠近栅极堆叠。 应变硅锗被原位掺杂并在沟道区域上产生纵向应力。

公开(公告)号：US07645656B2

公开(公告)日：2010-01-12

申请号：US11463777

申请日：2006-08-10

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner A. Rausch ,  Tsutomu Sato ,  Henry K. Utomo

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner A. Rausch ,  Tsutomu Sato ,  Henry K. Utomo

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28079 ,  H01L21/7624 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

摘要翻译： 提供场效应晶体管（“FET”），其包括覆盖衬底的单晶半导体区域的栅极堆叠，设置在所述栅极堆叠的侧壁上的一对第一间隔区，以及基本上由单个 晶体半导体合金，其设置在栅叠层的相对侧上。 每个半导体合金区域与栅极叠层隔开第一距离。 FET的源极区域和漏极区域至少部分地设置在半导体合金区域的相应半导体合金区域中，使得源极区域和漏极区域之间的距离与栅极叠层间隔开第二距离， 第一间隔物，第二距离与第一距离不同。

公开(公告)号：US07135724B2

公开(公告)日：2006-11-14

申请号：US10711637

申请日：2004-09-29

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner A. Rausch ,  Tsutomu Sato ,  Henry K. Utomo

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner A. Rausch ,  Tsutomu Sato ,  Henry K. Utomo

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28079 ,  H01L21/7624 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

摘要翻译： 提供场效应晶体管（“FET”），其包括覆盖衬底的单晶半导体区域的栅极堆叠，设置在所述栅极堆叠的侧壁上的一对第一间隔区，以及基本上由单个 晶体半导体合金，其设置在栅叠层的相对侧上。 每个半导体合金区域与栅极叠层隔开第一距离。 FET的源极区域和漏极区域至少部分地设置在半导体合金区域的相应半导体合金区域中，使得源极区域和漏极区域之间的距离与栅极叠层间隔开第二距离， 第一间隔物，第二距离与第一距离不同。

公开(公告)号：US07176481B2

公开(公告)日：2007-02-13

申请号：US10905598

申请日：2005-01-12

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Siddhartha Panda ,  Sang-Hyun Oh ,  Henry K. Utomo ,  Werner A. Rausch

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Siddhartha Panda ,  Sang-Hyun Oh ,  Henry K. Utomo ,  Werner A. Rausch

IPC分类号： H01L29/06

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

摘要： Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained epitaxial silicon germanium, wherein the strained silicon germanium comprises of two layers, with a top layer that is closer to the gate stack than the bottom layer. The strained silicon germanium is in-situ doped and creates longitudinal stress on the channel region.

摘要翻译： 公开了一种集成电路结构以及在衬底上具有衬底和P型和N型晶体管的结构的方法。 N型晶体管延伸和源极/漏极区域包括注入到衬底中的掺杂剂。 P型晶体管延伸和源极/漏极区域部分地包括应变外延硅锗，其中应变硅锗包括两层，顶层比底层更靠近栅极堆叠。 应变硅锗被原位掺杂并在沟道区域上产生纵向应力。

公开(公告)号：US20080258180A1

公开(公告)日：2008-10-23

申请号：US11306721

申请日：2006-01-09

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Judson R. Holt ,  Qiqing Ouyang ,  Siddhartha Panda

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Judson R. Holt ,  Qiqing Ouyang ,  Siddhartha Panda

IPC分类号： H01L29/78 ,  H01L29/04 ,  H01L21/336

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A semiconductor structure and a method for fabricating the semiconductor structure include a semiconductor substrate having a cross-section hourglass shaped channel region. A stress imparting layer is located adjacent the channel region. The hourglass shape may provide for enhanced vertical tensile stress within the channel region when it is longitudinally compressive stressed by the stress imparting layer.

摘要翻译： 半导体结构和制造半导体结构的方法包括具有横截面沙漏形沟道区域的半导体衬底。 应力施加层位于沟道区附近。 沙漏形状可以在通过应力施加层纵向压缩应力时提供通道区域内的增强的垂直拉伸应力。

公开(公告)号：US07863197B2

公开(公告)日：2011-01-04

申请号：US11306721

申请日：2006-01-09

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Judson R. Holt ,  Qiqing C. Ouyang ,  Siddhartha Panda

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Judson R. Holt ,  Qiqing C. Ouyang ,  Siddhartha Panda

IPC分类号： H01L21/302 ,  H01L21/00

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A method for fabricating the semiconductor structure include a semiconductor substrate having a cross-section hourglass shaped channel region. A stress imparting layer is located adjacent the channel region. The hourglass shape may provide for enhanced vertical tensile stress within the channel region when it is longitudinally compressive stressed by the stress imparting layer.

摘要翻译： 制造半导体结构的方法包括具有横截面沙漏形沟道区域的半导体衬底。 应力施加层位于沟道区附近。 沙漏形状可以在通过应力施加层纵向压缩应力时提供通道区域内的增强的垂直拉伸应力。

公开(公告)号：US07687829B2

公开(公告)日：2010-03-30

申请号：US12144250

申请日：2008-06-23

申请人： Dureseti Chidambarrao ,  Judson R. Holt ,  Meikei Ieong ,  Qiqing C. Ouyang ,  Siddhartha Panda

发明人： Dureseti Chidambarrao ,  Judson R. Holt ,  Meikei Ieong ,  Qiqing C. Ouyang ,  Siddhartha Panda

IPC分类号： H01L29/04

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L29/7843

摘要： A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.

摘要翻译： 提供了具有改进的载流子迁移率的半导体结构。 半导体结构包括具有不同晶体取向的至少两个平坦表面的混合取向半导体衬底，以及位于不同结晶取向的每个平面上的至少一个CMOS器件，其中每个CMOS器件具有应力通道。 本发明还提供了制造该方法的方法。 一般来说，本发明的方法包括提供具有至少两个具有不同晶体取向的平面表面的混合取向衬底，以及在不同结晶取向的每个平面上形成至少一个CMOS器件，其中每个CMOS器件具有受压沟道 。

公开(公告)号：US07776695B2

公开(公告)日：2010-08-17

申请号：US11306716

申请日：2006-01-09

申请人： John C. Arnold ,  Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Siddhartha Panda ,  Brian L. Tessier ,  Richard Wise

发明人： John C. Arnold ,  Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Siddhartha Panda ,  Brian L. Tessier ,  Richard Wise

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L27/0922 ,  H01L29/6656 ,  H01L29/7842 ,  H01L29/7843

摘要： A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.

摘要翻译： 一种制造半导体器件结构的方法，包括：提供衬底; 在衬底上形成具有第一间隔物的第一栅极，具有第二间隔物的第二栅极，与第一栅极和第二栅极相邻的相同导电类型的相应源极和漏极区域，设置在第一栅极和第二栅极之间的隔离区域 栅极，第一栅极上的硅化物，第二栅极和相应的源极和漏极区域; 在第一间隔物上形成附加间隔物以产生中间结构，然后在整个中间结构上设置应力层。