公开(公告)号：US20120313222A1

公开(公告)日：2012-12-13

申请号：US13178375

申请日：2011-07-07

申请人： Hung-Jen LEE ,  Shu-Ming CHANG ,  Chen-Han CHIANG ,  Tsang-Yu LIU ,  Yen-Shih HO

发明人： Hung-Jen LEE ,  Shu-Ming CHANG ,  Chen-Han CHIANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC分类号： H01L29/02 ,  H01L21/78

CPC分类号： H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

摘要： An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

摘要翻译： 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定在其上的多个预定划线的第一基板，其中，所述预定划线限定多个器件区域; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环和位于芯片支撑环的周边的切割支撑结构，并且间隔层具有 将切割支撑结构与芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一实施例提供一种芯片封装结构。

公开(公告)号：US20120313261A1

公开(公告)日：2012-12-13

申请号：US13492649

申请日：2012-06-08

申请人： Hung-Jen LEE ,  Shu-Ming CHANG ,  Chen-Han CHIANG ,  Tsang-Yu LIU ,  Yen-Shih HO

发明人： Hung-Jen LEE ,  Shu-Ming CHANG ,  Chen-Han CHIANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC分类号： H01L23/48 ,  H01L21/78

CPC分类号： H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

摘要： An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defining a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively, a cutting support structure located on peripheries of the chip support rings, a plurality of stop rings surrounding the chip support rings respectively, wherein a gap pattern separating the stop rings from the cutting support structure and the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

摘要翻译： 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定多个器件区域的多个预定划线的第一衬底; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环，位于芯片支撑环的周边的切割支撑结构，围绕 所述芯片支撑环分别具有将所述止动环与所述切割支撑结构和所述芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一实施例提供一种芯片封装结构。

公开(公告)号：US20120194301A1

公开(公告)日：2012-08-02

申请号：US13359460

申请日：2012-01-26

申请人： Ho-Yin YIU ,  Chien-Hung LIU ,  Ying-Nan WEN ,  Shih-Yi LEE ,  Wei-Chung YANG ,  Bai-Yao LOU ,  Hung-Jen LEE

发明人： Ho-Yin YIU ,  Chien-Hung LIU ,  Ying-Nan WEN ,  Shih-Yi LEE ,  Wei-Chung YANG ,  Bai-Yao LOU ,  Hung-Jen LEE

IPC分类号： H03H7/00 ,  H01P5/02

CPC分类号： H01L23/642 ,  H01L23/48 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/1901 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/014

摘要： Embodiments of the present invention provide a capacitive coupler packaging structure including a substrate with at least one capacitor and a receiver formed thereon, wherein the at least one capacitor at least includes a first electrode layer, a second electrode layer and a capacitor dielectric layer therebetween, and the first electrode layer is electrically connected to the receiver via a solder ball. The capacitive coupler packaging structure also includes a transmitter electrically connecting to the capacitor.

摘要翻译： 本发明的实施例提供一种电容耦合器封装结构，其包括具有至少一个电容器的基板和形成在其上的接收器，其中所述至少一个电容器至少包括第一电极层，第二电极层和电介质层之间， 并且第一电极层通过焊球电连接到接收器。 电容耦合器封装结构还包括电连接到电容器的发射器。