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公开(公告)号：US20120194301A1
公开(公告)日：2012-08-02
申请号：US13359460
申请日：2012-01-26
申请人： Ho-Yin YIU , Chien-Hung LIU , Ying-Nan WEN , Shih-Yi LEE , Wei-Chung YANG , Bai-Yao LOU , Hung-Jen LEE
发明人： Ho-Yin YIU , Chien-Hung LIU , Ying-Nan WEN , Shih-Yi LEE , Wei-Chung YANG , Bai-Yao LOU , Hung-Jen LEE
CPC分类号： H01L23/642 , H01L23/48 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L2224/13101 , H01L2224/16225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49175 , H01L2924/00014 , H01L2924/01327 , H01L2924/1901 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2924/014
摘要： Embodiments of the present invention provide a capacitive coupler packaging structure including a substrate with at least one capacitor and a receiver formed thereon, wherein the at least one capacitor at least includes a first electrode layer, a second electrode layer and a capacitor dielectric layer therebetween, and the first electrode layer is electrically connected to the receiver via a solder ball. The capacitive coupler packaging structure also includes a transmitter electrically connecting to the capacitor.
摘要翻译： 本发明的实施例提供一种电容耦合器封装结构，其包括具有至少一个电容器的基板和形成在其上的接收器，其中所述至少一个电容器至少包括第一电极层，第二电极层和电介质层之间， 并且第一电极层通过焊球电连接到接收器。 电容耦合器封装结构还包括电连接到电容器的发射器。
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公开(公告)号：US20120146153A1
公开(公告)日：2012-06-14
申请号：US13314114
申请日：2011-12-07
申请人： Ying-Nan WEN , Ho-Yin YIU , Yen-Shih HO , Shu-Ming CHANG , Chien-Hung LIU , Shih-Yi LEE , Wei-Chung YANG
发明人： Ying-Nan WEN , Ho-Yin YIU , Yen-Shih HO , Shu-Ming CHANG , Chien-Hung LIU , Shih-Yi LEE , Wei-Chung YANG
IPC分类号： H01L27/092 , H01L21/28 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/3114 , H01L23/3185 , H01L23/481 , H01L24/05 , H01L24/13 , H01L2221/68327 , H01L2221/6834 , H01L2221/6835 , H01L2221/68363 , H01L2224/02372 , H01L2224/03464 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/05567 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05666 , H01L2224/05669 , H01L2224/05672 , H01L2224/11002 , H01L2224/13007 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/96 , H01L2924/00013 , H01L2924/00014 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/014 , H01L2224/03 , H01L2224/11 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552
摘要： A chip package includes: a substrate; a drain and a source regions located in the substrate; a gate located on or buried in the substrate; a drain conducting structure, a source conducting structure, and a gate conducting structure, disposed on the substrate and electrically connected to the drain region, the source region, and the gate, respectively; a second substrate disposed beside the substrate; a second drain and a second source region located in the second substrate, wherein the second drain region is electrically connected to the source region; a second gate located on or buried in the second substrate; and a second source and a second gate conducting structure disposed on the second substrate and electrically connected to the second source region and the second gate, respectively, wherein terminal points of the drain, the source, the gate, the second source, and the second gate conducting structures are substantially coplanar.
摘要翻译： 芯片封装包括：基板; 位于衬底中的漏极和源极区域; 位于衬底上或埋在衬底中的门; 漏极导电结构，源极导电结构和栅极导电结构，分别设置在所述衬底上并电连接到所述漏极区域，所述源极区域和所述栅极; 设置在所述基板旁边的第二基板; 位于所述第二基板中的第二漏极和第二源极区域，其中所述第二漏极区域电连接到所述源极区域; 位于第二基板上或埋在第二基板中的第二栅极; 以及第二源极和第二栅极导电结构，其设置在所述第二基板上并分别电连接到所述第二源极区域和所述第二栅极，其中所述漏极，所述源极，所述栅极，所述第二源极和所述第二栅极的端点 栅极导电结构基本上共面。
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公开(公告)号：US08791768B2
公开(公告)日：2014-07-29
申请号：US13359460
申请日：2012-01-26
申请人： Ho-Yin Yiu , Chien-Hung Liu , Ying-Nan Wen , Shih-Yi Lee , Wei-Chung Yang , Bai-Yao Lou , Hung-Jen Lee
发明人： Ho-Yin Yiu , Chien-Hung Liu , Ying-Nan Wen , Shih-Yi Lee , Wei-Chung Yang , Bai-Yao Lou , Hung-Jen Lee
CPC分类号： H01L23/642 , H01L23/48 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L2224/13101 , H01L2224/16225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49175 , H01L2924/00014 , H01L2924/01327 , H01L2924/1901 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2924/014
摘要： Embodiments of the present invention provide a capacitive coupler packaging structure including a substrate with at least one capacitor and a receiver formed thereon, wherein the at least one capacitor at least includes a first electrode layer, a second electrode layer and a capacitor dielectric layer therebetween, and the first electrode layer is electrically connected to the receiver via a solder ball. The capacitive coupler packaging structure also includes a transmitter electrically connecting to the capacitor.
摘要翻译： 本发明的实施例提供一种电容耦合器封装结构，其包括具有至少一个电容器的基板和形成在其上的接收器，其中所述至少一个电容器至少包括第一电极层，第二电极层和电介质层之间， 并且第一电极层通过焊球电连接到接收器。 电容耦合器封装结构还包括电连接到电容器的发射器。
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公开(公告)号：US08614488B2
公开(公告)日：2013-12-24
申请号：US13314114
申请日：2011-12-07
申请人： Ying-Nan Wen , Ho-Yin Yiu , Yen-Shih Ho , Shu-Ming Chang , Chien-Hung Liu , Shih-Yi Lee , Wei-Chung Yang
发明人： Ying-Nan Wen , Ho-Yin Yiu , Yen-Shih Ho , Shu-Ming Chang , Chien-Hung Liu , Shih-Yi Lee , Wei-Chung Yang
IPC分类号： H01L21/70
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/3114 , H01L23/3185 , H01L23/481 , H01L24/05 , H01L24/13 , H01L2221/68327 , H01L2221/6834 , H01L2221/6835 , H01L2221/68363 , H01L2224/02372 , H01L2224/03464 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/05567 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05666 , H01L2224/05669 , H01L2224/05672 , H01L2224/11002 , H01L2224/13007 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/96 , H01L2924/00013 , H01L2924/00014 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/014 , H01L2224/03 , H01L2224/11 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552
摘要： A chip package includes: a substrate; a drain and a source regions located in the substrate; a gate located on or buried in the substrate; a drain conducting structure, a source conducting structure, and a gate conducting structure, disposed on the substrate and electrically connected to the drain region, the source region, and the gate, respectively; a second substrate disposed beside the substrate; a second drain and a second source region located in the second substrate, wherein the second drain region is electrically connected to the source region; a second gate located on or buried in the second substrate; and a second source and a second gate conducting structure disposed on the second substrate and electrically connected to the second source region and the second gate, respectively, wherein terminal points of the drain, the source, the gate, the second source, and the second gate conducting structures are substantially coplanar.
摘要翻译： 芯片封装包括：基板; 位于衬底中的漏极和源极区域; 位于衬底上或埋在衬底中的门; 漏极导电结构，源极导电结构和栅极导电结构，分别设置在所述衬底上并电连接到所述漏极区域，所述源极区域和所述栅极; 设置在所述基板旁边的第二基板; 位于所述第二基板中的第二漏极和第二源极区域，其中所述第二漏极区域电连接到所述源极区域; 位于第二基板上或埋在第二基板中的第二栅极; 以及第二源极和第二栅极导电结构，其设置在所述第二基板上并分别电连接到所述第二源极区域和所述第二栅极，其中所述漏极，所述源极，所述栅极，所述第二源极和所述第二栅极的端点 栅极导电结构基本上共面。
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