公开(公告)号：US07903187B2

公开(公告)日：2011-03-08

申请号：US11635501

申请日：2006-12-08

申请人： Hyun Soo Shin ,  Yeon Gon Mo ,  Jae Kyeong Jeong ,  Se Yeoul Kwon

发明人： Hyun Soo Shin ,  Yeon Gon Mo ,  Jae Kyeong Jeong ,  Se Yeoul Kwon

IPC分类号： G02F1/1333 ,  H01L27/13

CPC分类号： H01L27/0248 ,  G02F1/136204 ,  H01L27/12 ,  H01L27/3244 ,  H01L27/3276

摘要： A static electricity preventing assembly for an electronic device, may include a substrate, a buffer layer on the substrate, the buffer layer including a plurality of contact holes exposing respective regions of the substrate, a shorting bar on the buffer layer, pad electrodes on the buffer layer, metal wiring lines on the buffer layer, wherein a first portion of each of the metal wiring lines may be electrically connected to the substrate through the contact holes, a second portion of each of the metal wiring lines may be connected to a respective one of the pad electrodes, and a third portion of each of the metal wiring lines may be connected to the shorting bar, wherein the first portion may be between the second portion and the third portion.

摘要翻译： 一种用于电子设备的静电防止组件可以包括衬底，衬底上的缓冲层，缓冲层包括暴露衬底各自区域的多个接触孔，缓冲层上的短路棒， 缓冲层，缓冲层上的金属布线，其中每个金属布线的第一部分可以通过接触孔电连接到基板，每个金属布线的第二部分可以连接到相应的 焊盘电极中的一个，并且每个金属布线的第三部分可以连接到短路棒，其中第一部分可以在第二部分和第三部分之间。

公开(公告)号：US07803699B2

公开(公告)日：2010-09-28

申请号：US11507606

申请日：2006-08-22

申请人： Jae Kyeong Jeong ,  Hyun Soo Shin ,  Yeon Gon Mo

发明人： Jae Kyeong Jeong ,  Hyun Soo Shin ,  Yeon Gon Mo

IPC分类号： H01L21/20

CPC分类号： H01L21/02686 ,  H01L21/02532 ,  H01L21/2026 ,  H01L29/66757 ,  H01L29/66765

摘要： A polysilicon thin film transistor (TFT) may include a substrate, at least one insulating layer, a semiconductor layer, a gate electrode, a source electrode, a drain electrode, and a heat retaining layer formed to contact the semiconductor layer. The heat retaining layer may reduce and/or prevent a reduction in a melt duration time of amorphous silicon during a crystallization process for forming a polysilicon layer of the TFT.

摘要翻译： 多晶硅薄膜晶体管（TFT）可以包括基板，至少一个绝缘层，半导体层，栅电极，源电极，漏电极和形成为接触半导体层的保温层。 在用于形成TFT的多晶硅层的结晶工艺期间，保温层可以减少和/或防止非晶硅的熔融持续时间的减少。

公开(公告)号：US07463399B2

公开(公告)日：2008-12-09

申请号：US11528414

申请日：2006-09-28

申请人： Hyun Soo Shin ,  Jae Kyeong Jeong ,  Yeon Gon Mo ,  Dong Un Jin

发明人： Hyun Soo Shin ,  Jae Kyeong Jeong ,  Yeon Gon Mo ,  Dong Un Jin

IPC分类号： G02F1/15 ,  G02F1/153 ,  G09G3/34 ,  G09G5/00

CPC分类号： H01L27/3244 ,  G02F1/167 ,  G02F2001/133342 ,  H01L27/3232 ,  H01L2251/5323

摘要： The flat panel display includes an electrochromic device that is a controlling unit. The electrochromic device reversibly makes electrolytic oxidizing and reducing reactions so that coloring and decoloring can be made reversibly, when voltage is applied. With such the construction, the flat panel display controls the voltage applied to the electrochromic device, enabling to selectively display an image on front side or two sides.

摘要翻译： 平板显示器包括作为控制单元的电致变色装置。 电致变色装置可逆地进行电解氧化和还原反应，使得当施加电压时可以可逆地着色和脱色。 通过这样的结构，平板显示器控制施加到电致变色装置的电压，能够在前侧或两侧选择性地显示图像。

公开(公告)号：US07084039B2

公开(公告)日：2006-08-01

申请号：US11024792

申请日：2004-12-30

申请人： Hyun Soo Shin

发明人： Hyun Soo Shin

IPC分类号： H01L21/331

CPC分类号： H01L21/823878 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823892

摘要： A method of fabricating a CMOS (complementary metal oxide semiconductor) transistor includes manufacturing steps, by which adverse transistor characteristics can be prevented from being degraded by high-temperature annealing for hardening a screen oxide layer. The method includes steps of forming a gate on a semiconductor substrate with a gate oxide layer therebetween, forming a screen oxide layer on the substrate and the gate, forming a nitride layer on the screen oxide layer, forming LDD regions in the substrate substantially aligned with the gate, removing the nitride layer, forming a spacer on the screen oxide layer and on at least a portion of a sidewall of the gate, and forming in the substrate source/drain regions extending from the LDD regions respectively in the substrate substantially aligned with the spacer.

摘要翻译： 制造CMOS（互补金属氧化物半导体）晶体管的方法包括制造步骤，由此通过用于硬化屏幕氧化物层的高温退火可以防止不利的晶体管特性劣化。 该方法包括以下步骤：在半导体衬底上形成栅极氧化层之间的栅极，在衬底和栅极上形成屏蔽氧化物层，在栅极氧化层上形成氮化物层，在衬底中形成基本上与 栅极，去除氮化物层，在屏幕氧化物层上和栅极的侧壁的至少一部分上形成间隔物，并且在基板上形成基板源极/漏极区域，该基板源极/漏极区域分别从基板上的LDD区域延伸，基本上与 间隔物。

公开(公告)号：US07663302B2

公开(公告)日：2010-02-16

申请号：US11493576

申请日：2006-07-27

申请人： Hyun Soo Shin ,  Jae Kyeong Jeong ,  Yeon Gon Mo ,  Dong Un Jin

发明人： Hyun Soo Shin ,  Jae Kyeong Jeong ,  Yeon Gon Mo ,  Dong Un Jin

IPC分类号： H05B33/00

CPC分类号： H01L51/5281 ,  H01L27/3244 ,  H01L2251/5323

摘要： An Organic Light Emitting Display (OLED) and its method of fabrication includes: a transparent substrate; a photochromatic layer formed on a first surface of the transparent substrate; at least one transparent Thin Film Transistor (TFT) formed on a first surface of the transparent substrate, and an organic light emitting device formed on and electrically connected to the transparent TFT.

摘要翻译： 有机发光显示器（OLED）及其制造方法包括：透明基板; 在所述透明基板的第一表面上形成的色素层; 形成在透明基板的第一表面上的至少一个透明薄膜晶体管（TFT）和形成在透明TFT上并电连接到透明TFT的有机发光器件。

公开(公告)号：US07655951B2

公开(公告)日：2010-02-02

申请号：US11433177

申请日：2006-05-12

申请人： Jae Kyeong Jeong ,  Jae Bon Koo ,  Hyun Soo Shin ,  Yeon Gon Mo

发明人： Jae Kyeong Jeong ,  Jae Bon Koo ,  Hyun Soo Shin ,  Yeon Gon Mo

IPC分类号： H01L29/786

CPC分类号： H01L29/78603 ,  H01L29/66757 ,  H01L29/78675

摘要： A thin film transistor and a method for manufacturing the same capable of reducing a change in a threshold voltage of the thin film transistor formed on a flexible substrate. The thin film transistor includes: a substrate, the substrate being flexible; a buffer layer having a low dielectric constant from about 1.2 to about 4.0 and formed on the substrate; a semiconductor layer formed on the buffer layer; a gate electrode; first insulation layer formed between the gate electrode and the semiconductor layer; a second insulation layer formed on the semiconductor layer and the gate electrode; and a source/drain electrode electrically connected to the semiconductor layer through a contact hole formed in the second insulation layer. Therefore, the thin film transistor can reduce a change in its threshold voltage, thereby reducing changes in brightness, gray scale, contrast, etc., of light-emitting devices using the thin film transistor.

摘要翻译： 一种薄膜晶体管及其制造方法，能够减小形成在柔性基板上的薄膜晶体管的阈值电压的变化。 所述薄膜晶体管包括：基板，所述基板是柔性的; 缓冲层，其介电常数为约1.2至约4.0，并形成在基底上; 形成在缓冲层上的半导体层; 栅电极; 形成在所述栅电极和所述半导体层之间的第一绝缘层; 形成在所述半导体层和所述栅电极上的第二绝缘层; 以及源极/漏极，其通过形成在第二绝缘层中的接触孔与半导体层电连接。 因此，薄膜晶体管可以减小其阈值电压的变化，从而减少使用薄膜晶体管的发光器件的亮度，灰度，对比度等的变化。

公开(公告)号：US20080274575A1

公开(公告)日：2008-11-06

申请号：US12216015

申请日：2008-06-27

申请人： Hyun Soo Shin ,  Kyu-Ho Shin ,  Jae-Hee Cho

发明人： Hyun Soo Shin ,  Kyu-Ho Shin ,  Jae-Hee Cho

IPC分类号： H01L33/00

CPC分类号： H01L33/0079 ,  B82Y20/00 ,  H01S5/0217 ,  H01S5/183 ,  H01S5/34333

摘要： Provided is a vertical semiconductor light-emitting device and a method of manufacturing the same. The method may include sequentially forming a lower clad layer, an active layer, and an upper clad layer on a substrate to form a semiconductor layer and forming first electrode layers on the upper clad layer. A metal support layer may be formed on each of the first electrode layers and a trench may be formed between the first electrode layers. The substrate may be removed and a second electrode layer may be formed on the lower clad layer.

摘要翻译： 提供了一种垂直半导体发光器件及其制造方法。 该方法可以包括在衬底上顺序地形成下覆盖层，有源层和上覆盖层，以形成半导体层，并在上覆盖层上形成第一电极层。 可以在每个第一电极层上形成金属支撑层，并且可以在第一电极层之间形成沟槽。 可以去除衬底，并且可以在下包层上形成第二电极层。

公开(公告)号：US20140239292A1

公开(公告)日：2014-08-28

申请号：US14127690

申请日：2011-11-22

申请人： Hyun Jae Kim ,  Hyun Soo Shin ,  You Seung Rim

发明人： Hyun Jae Kim ,  Hyun Soo Shin ,  You Seung Rim

IPC分类号： H01L21/02 ,  H01L29/24

CPC分类号： H01L21/02565 ,  H01L21/02422 ,  H01L21/02554 ,  H01L21/02628 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869

摘要： Provided are a method of forming an oxide thin film and an electrical device and thin film transistor using the method. The method includes forming an oxide thin film on a substrate by applying a precursor solution; and performing a thermal treatment process on the substrate under a pressurized atmosphere using a gas at about 100° C. to about 400° C.

摘要翻译： 提供了使用该方法形成氧化物薄膜的方法和电子器件和薄膜晶体管。 该方法包括通过施加前体溶液在衬底上形成氧化物薄膜; 并且在加压气氛下使用约100℃至约400℃的气体在基板上进行热处理过程。

公开(公告)号：US07704814B2

公开(公告)日：2010-04-27

申请号：US11498680

申请日：2006-08-02

申请人： Hyun Soo Shin ,  Jae Won Han

发明人： Hyun Soo Shin ,  Jae Won Han

IPC分类号： H01L21/336

CPC分类号： H01L21/823493 ,  H01L29/6659 ,  H01L29/7833

摘要： Disclosed is a method for manufacturing a semiconductor device including a low-voltage MOS transistor and a high-voltage MOS transistor. The present method includes a low-voltage well implantation process on a semiconductor substrate to form a first well in a first region of the substrate and a second well in a second region of the substrate; forming first and second gate oxide layers and first and second gate electrodes in the first and second regions, respectively; forming a first photoresist pattern to expose the first region; forming a first LDD region in the first region exposed by the first photoresist pattern and the first gate electrode; removing the first photoresist pattern; forming a second photoresist pattern to expose the second region; forming a second LDD region in the second region exposed by the second photoresist pattern and the second gate electrode; performing a compensational implantation on the second region to adjust a well concentration for the high-voltage MOS transistor; and removing the second photoresist pattern.

摘要翻译： 公开了一种制造包括低电压MOS晶体管和高压MOS晶体管的半导体器件的方法。 本方法包括在半导体衬底上的低电压阱注入工艺，以在衬底的第一区域中形成第一阱，在衬底的第二区域中形成第二阱; 分别在第一和第二区域中形成第一和第二栅极氧化物层和第一和第二栅电极; 形成第一光致抗蚀剂图案以暴露第一区域; 在由第一光致抗蚀剂图案和第一栅电极暴露的第一区域中形成第一LDD区; 去除第一光致抗蚀剂图案; 形成第二光致抗蚀剂图案以暴露所述第二区域; 在由所述第二光致抗蚀剂图案和所述第二栅电极暴露的所述第二区域中形成第二LDD区域; 在所述第二区域上执行补偿注入以调整所述高压MOS晶体管的阱浓度; 并且去除第二光致抗蚀剂图案。

公开(公告)号：US5646881A

公开(公告)日：1997-07-08

申请号：US588242

申请日：1996-01-18

申请人： Yi Hwan Park ,  Hyun Soo Shin ,  Yong-Bok Lee

发明人： Yi Hwan Park ,  Hyun Soo Shin ,  Yong-Bok Lee

IPC分类号： G11C11/404 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4096 ,  G11C11/24

CPC分类号： G11C11/4096 ,  G11C11/406

摘要： In a DRAM cell, as a word line signal is applied to a gate of a MOS transistor, the MOS transistor writes the voltage applied to bit lines BL and BL into a capacitor. When a high level data is written, a voltage of the bit line BL or BL is increased to be higher than a power supply voltage, so as to permit reading of the data in a stable condition. When a capacitance value of the cell is the same as that of the conventional art, a refresh time of the present semiconductor memory, e.g., DRAM memory, is lengthened over that of the conventional art, whereas when the refresh time is the same as that of the conventional art, the capacitance value used in the present semiconductor memory can be reduced from that of the conventional art.

摘要翻译： 在DRAM单元中，当MOS晶体管的栅极被施加字线信号时，MOS晶体管将施加到位线BL和+ E，ovs BL + EE的电压写入电容器。 当写入高电平数据时，位线BL或+ E，ovs BL + EE的电压增加到高于电源电压，以便允许在稳定状态下读取数据。 当单元的电容值与常规技术的电容值相同时，本发明半导体存储器（例如DRAM存储器）的刷新时间比常规技术的刷新时间延长，而当刷新时间与现有技术相同时 在现有的半导体存储器中使用的电容值可以比传统技术中减少。