公开(公告)号：US08362536B2

公开(公告)日：2013-01-29

申请号：US12904344

申请日：2010-10-14

申请人： Hyung-woo Chung ,  Yong-chul Oh ,  Yoo-sang Hwang ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Dae-ik Kim

发明人： Hyung-woo Chung ,  Yong-chul Oh ,  Yoo-sang Hwang ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Dae-ik Kim

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10805 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10885

摘要： A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.

摘要翻译： 半导体存储器件包括从衬底延伸以形成垂直沟道区的第一对柱，所述第一对柱具有彼此相邻的第一柱和第二柱，所述第一柱和第二柱以第一方向 ，设置在形成在所述第一对柱之间的第一沟槽的底表面上的第一位线，所述第一位线在基本上垂直于所述第一方向的第二方向上延伸;第一接触栅极，设置在第一表面上， 所述第一支柱具有第一栅极绝缘层，第二触点栅极，设置在所述第二支柱的第一表面上，第二栅极绝缘层之间具有第二栅极绝缘层，所述第一支柱的第一表面和所述第二支柱的第一表面面向相反方向 以及设置在第一接触栅极上的第一字线和设置在第二接触栅极上的第二字线，在fi 第一个方向。

公开(公告)号：US08492832B2

公开(公告)日：2013-07-23

申请号：US13571805

申请日：2012-08-10

申请人： Ji-young Kim ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Yoo-sang Hwang ,  Sung-kwan Choi ,  Hyun-woo Chung

发明人： Ji-young Kim ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Yoo-sang Hwang ,  Sung-kwan Choi ,  Hyun-woo Chung

IPC分类号： H01L29/78

CPC分类号： H01L27/10876 ,  H01L27/10823 ,  H01L29/4236

摘要： A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation layer, a trench extending across the active region, a buried gate filling a part of the trench and including a base portion, a first extension portion, and a second extension portion extending along an inner wall of the trench, and having different heights at sides of the base portion, and a capping layer formed on the buried gate and filling the trench.

摘要翻译： 半导体器件包括半导体衬底，其包括由器件隔离层限定的有源区，横跨有源区延伸的沟槽，填充沟槽的一部分并包括基部的掩埋栅，第一延伸部和第二延伸部 沿着沟槽的内壁延伸的部分，并且在基部的侧面具有不同的高度，以及形成在掩埋栅极上并填充沟槽的覆盖层。

公开(公告)号：US20130037882A1

公开(公告)日：2013-02-14

申请号：US13571805

申请日：2012-08-10

申请人： Ji-young Kim ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Yoo-sang Hwang ,  Sung-kwan Choi ,  Hyun-woo Chung

发明人： Ji-young Kim ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Yoo-sang Hwang ,  Sung-kwan Choi ,  Hyun-woo Chung

IPC分类号： H01L29/78

CPC分类号： H01L27/10876 ,  H01L27/10823 ,  H01L29/4236

摘要： A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation layer, a trench extending across the active region, a buried gate filling a part of the trench and including a base portion, a first extension portion, and a second extension portion extending along an inner wall of the trench, and having different heights at sides of the base portion, and a capping layer formed on the buried gate and filling the trench.

摘要翻译： 半导体器件包括半导体衬底，其包括由器件隔离层限定的有源区，横跨有源区延伸的沟槽，填充沟槽的一部分并包括基部的掩埋栅，第一延伸部和第二延伸部 沿着沟槽的内壁延伸的部分，并且在基部的侧面具有不同的高度，以及形成在掩埋栅极上并填充沟槽的覆盖层。

公开(公告)号：US08264022B2

公开(公告)日：2012-09-11

申请号：US12588790

申请日：2009-10-28

申请人： Jae-man Yoon ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Makoto Yoshida ,  Bong-soo Kim

发明人： Jae-man Yoon ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Makoto Yoshida ,  Bong-soo Kim

IPC分类号： H01L21/70 ,  H01L21/8246 ,  H01L27/22

CPC分类号： H01L21/76834 ,  H01L21/76816 ,  H01L23/485 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/11 ,  H01L27/11517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and associated methods, the semiconductor device including a semiconductor layer including a first region and a second region, a first contact plug disposed on the semiconductor layer and electrically connected to the first region, a second contact plug disposed on the semiconductor layer and electrically connected to the second region, a conductive layer electrically connected to the first contact plug, the conductive layer having a side surface and a bottom surface, and an insulating layer disposed between the conductive layer and the second contact plug so as to insulate the conductive layer from the second contact plug, the insulating layer facing the side surface and a portion of the bottom surface of the conductive layer.

摘要翻译： 一种半导体器件及相关方法，所述半导体器件包括包括第一区域和第二区域的半导体层，设置在半导体层上并与第一区域电连接的第一接触插塞，设置在半导体层上的第二接触插塞和 电连接到第二区域，导电层电连接到第一接触插塞，导电层具有侧表面和底表面，以及绝缘层，设置在导电层和第二接触插塞之间，以使导电 层，所述绝缘层面向所述导电层的侧表面和所述底表面的一部分。

公开(公告)号：US07501668B2

公开(公告)日：2009-03-10

申请号：US11582926

申请日：2006-10-18

申请人： Se-Myeong Jang ,  Yong-chul Oh ,  Gyo-young Jin

发明人： Se-Myeong Jang ,  Yong-chul Oh ,  Gyo-young Jin

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L27/10855 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/105 ,  H01L27/10817 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device having a semiconductor substrate includes a gate structure on the semiconductor substrate. Source/drain regions are on opposite sides of the gate structure. A contact pad is on at least one of the source/drain region, and a silicide cap is on a surface of the contact pad opposite the respective source/drain region.

摘要翻译： 具有半导体衬底的集成电路器件包括半导体衬底上的栅极结构。 源极/漏极区位于栅极结构的相对侧。 接触焊盘位于源极/漏极区域中的至少一个上，并且硅化物帽位于与相应源极/漏极区域相对的接触焊盘的表面上。

公开(公告)号：US20070037375A1

公开(公告)日：2007-02-15

申请号：US11582926

申请日：2006-10-18

申请人： Se-Myeong Jang ,  Yong-chul Oh ,  Gyo-young Jin

发明人： Se-Myeong Jang ,  Yong-chul Oh ,  Gyo-young Jin

IPC分类号： H01L21/44

CPC分类号： H01L27/10855 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/105 ,  H01L27/10817 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device having a semiconductor substrate includes a gate structure on the semiconductor substrate. Source/drain regions are on opposite sides of the gate structure. A contact pad is on at least one of the source/drain region, and a silicide cap is on a surface of the contact pad opposite the respective source/drain region.

摘要翻译： 具有半导体衬底的集成电路器件包括半导体衬底上的栅极结构。 源极/漏极区位于栅极结构的相对侧。 接触焊盘位于源极/漏极区域中的至少一个上，并且硅化物帽位于与相应源极/漏极区域相对的接触焊盘的表面上。

公开(公告)号：US20100207241A1

公开(公告)日：2010-08-19

申请号：US12588790

申请日：2009-10-28

申请人： Jae-man Yoon ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Makoto Yoshida ,  Bong-soo Kim

发明人： Jae-man Yoon ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Makoto Yoshida ,  Bong-soo Kim

IPC分类号： H01L23/485 ,  H01L29/92

CPC分类号： H01L21/76834 ,  H01L21/76816 ,  H01L23/485 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/11 ,  H01L27/11517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and associated methods, the semiconductor device including a semiconductor layer including a first region and a second region, a first contact plug disposed on the semiconductor layer and electrically connected to the first region, a second contact plug disposed on the semiconductor layer and electrically connected to the second region, a conductive layer electrically connected to the first contact plug, the conductive layer having a side surface and a bottom surface, and an insulating layer disposed between the conductive layer and the second contact plug so as to insulate the conductive layer from the second contact plug, the insulating layer facing the side surface and a portion of the bottom surface of the conductive layer.

摘要翻译： 一种半导体器件和相关方法，所述半导体器件包括包括第一区域和第二区域的半导体层，设置在半导体层上并电连接到第一区域的第一接触插塞，设置在半导体层上的第二接触插塞和 电连接到第二区域，导电层电连接到第一接触插塞，导电层具有侧表面和底表面，以及绝缘层，设置在导电层和第二接触插塞之间，以使导电 层，所述绝缘层面向所述导电层的侧表面和所述底表面的一部分。

公开(公告)号：US20080001235A1

公开(公告)日：2008-01-03

申请号：US11853361

申请日：2007-09-11

申请人： Se-myeong Jang ,  Gyo-young Jin ,  Yong-chul Oh ,  Hyun-chang Kim

发明人： Se-myeong Jang ,  Gyo-young Jin ,  Yong-chul Oh ,  Hyun-chang Kim

IPC分类号： H01L29/78

CPC分类号： H01L29/41783 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/823418 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628

摘要： Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is provided on the portion of the barrier layer spacer protruding from the sidewalls of the gate.

摘要翻译： 提供集成电路器件，其包括集成电路衬底和集成电路衬底上的栅极。 门有侧壁。 阻挡层间隔件设置在栅极的侧壁上。 阻挡层间隔物的一部分从栅极的侧壁突出，暴露出面向集成电路基板的阻挡层隔离物的下表面。 在从栅极的侧壁突出的阻挡层隔离物的部分上提供硅化物层。

公开(公告)号：US06974752B2

公开(公告)日：2005-12-13

申请号：US10422430

申请日：2003-04-24

申请人： Se-myeong Jang ,  Gyo-young Jin ,  Yong-chul Oh ,  Hyun-chang Kim

发明人： Se-myeong Jang ,  Gyo-young Jin ,  Yong-chul Oh ,  Hyun-chang Kim

IPC分类号： H01L21/8238 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/41783 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/823418 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628

摘要： A gate having sidewalls is formed on an integrated circuit substrate. A barrier layer spacer is formed on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is formed on the portion of the barrier layer spacer protruding from the sidewalls of the gate. Related devices are also provided.

摘要翻译： 具有侧壁的栅极形成在集成电路基板上。 在栅极的侧壁上形成阻挡层间隔物。 阻挡层间隔物的一部分从栅极的侧壁突出，暴露出面向集成电路基板的阻挡层隔离物的下表面。 在从栅极的侧壁突出的阻挡层隔离物的部分上形成硅化物层。 还提供了相关设备。

公开(公告)号：US20050255653A1

公开(公告)日：2005-11-17

申请号：US11166979

申请日：2005-06-24

申请人： Se-myeong Jang ,  Gyo-young Jin ,  Yong-chul Oh ,  Hyun-chang Kim

发明人： Se-myeong Jang ,  Gyo-young Jin ,  Yong-chul Oh ,  Hyun-chang Kim

IPC分类号： H01L21/8238 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/41783 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/823418 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628

摘要： Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is provided on the portion of the barrier layer spacer protruding from the sidewalls of the gate.

摘要翻译： 提供集成电路器件，其包括集成电路衬底和集成电路衬底上的栅极。 门有侧壁。 阻挡层间隔件设置在栅极的侧壁上。 阻挡层间隔物的一部分从栅极的侧壁突出，暴露出面向集成电路基板的阻挡层隔离物的下表面。 在从栅极的侧壁突出的阻挡层隔离物的部分上提供硅化物层。