公开(公告)号：US08884340B2

公开(公告)日：2014-11-11

申请号：US13298644

申请日：2011-11-17

申请人： Ji-Young Kim ,  Gyo-Young Jin ,  Hyeong-Sun Hong ,  Yong-Chul Oh ,  Yoo-Sang Hwang ,  Sung-Kwan Choi ,  Dong-Soo Woo ,  Hyun-Woo Chung

发明人： Ji-Young Kim ,  Gyo-Young Jin ,  Hyeong-Sun Hong ,  Yong-Chul Oh ,  Yoo-Sang Hwang ,  Sung-Kwan Choi ,  Dong-Soo Woo ,  Hyun-Woo Chung

IPC分类号： H01L21/336 ,  H01L29/772 ,  G11C11/404 ,  H01L27/108 ,  H01L29/66 ,  H01L29/78 ,  G11C11/408 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8234

CPC分类号： G11C11/4096 ,  G11C11/404 ,  G11C11/4085 ,  H01L21/823437 ,  H01L27/10823 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

摘要： A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.

摘要翻译： 半导体器件可以包括具有限定其间的沟道区的第一和第二间隔开的源极/漏极区的半导体衬底，以及在第一和第二间隔开的源极/漏极区之间的沟道区上的控制栅极结构。 更具体地，控制栅极结构可以包括在与第一源极/漏极区域相邻的沟道区域上的第一栅极电极以及与第二源极/漏极区域相邻的沟道区域上的第二栅极电极。 此外，第一和第二栅电极可以是电隔离的。 还讨论了相关设备，结构，操作方法和制造方法。

公开(公告)号：US08362536B2

公开(公告)日：2013-01-29

申请号：US12904344

申请日：2010-10-14

申请人： Hyung-woo Chung ,  Yong-chul Oh ,  Yoo-sang Hwang ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Dae-ik Kim

发明人： Hyung-woo Chung ,  Yong-chul Oh ,  Yoo-sang Hwang ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Dae-ik Kim

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10805 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10885

摘要： A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.

摘要翻译： 半导体存储器件包括从衬底延伸以形成垂直沟道区的第一对柱，所述第一对柱具有彼此相邻的第一柱和第二柱，所述第一柱和第二柱以第一方向 ，设置在形成在所述第一对柱之间的第一沟槽的底表面上的第一位线，所述第一位线在基本上垂直于所述第一方向的第二方向上延伸;第一接触栅极，设置在第一表面上， 所述第一支柱具有第一栅极绝缘层，第二触点栅极，设置在所述第二支柱的第一表面上，第二栅极绝缘层之间具有第二栅极绝缘层，所述第一支柱的第一表面和所述第二支柱的第一表面面向相反方向 以及设置在第一接触栅极上的第一字线和设置在第二接触栅极上的第二字线，在fi 第一个方向。

公开(公告)号：US08264022B2

公开(公告)日：2012-09-11

申请号：US12588790

申请日：2009-10-28

申请人： Jae-man Yoon ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Makoto Yoshida ,  Bong-soo Kim

发明人： Jae-man Yoon ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Makoto Yoshida ,  Bong-soo Kim

IPC分类号： H01L21/70 ,  H01L21/8246 ,  H01L27/22

CPC分类号： H01L21/76834 ,  H01L21/76816 ,  H01L23/485 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/11 ,  H01L27/11517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and associated methods, the semiconductor device including a semiconductor layer including a first region and a second region, a first contact plug disposed on the semiconductor layer and electrically connected to the first region, a second contact plug disposed on the semiconductor layer and electrically connected to the second region, a conductive layer electrically connected to the first contact plug, the conductive layer having a side surface and a bottom surface, and an insulating layer disposed between the conductive layer and the second contact plug so as to insulate the conductive layer from the second contact plug, the insulating layer facing the side surface and a portion of the bottom surface of the conductive layer.

摘要翻译： 一种半导体器件及相关方法，所述半导体器件包括包括第一区域和第二区域的半导体层，设置在半导体层上并与第一区域电连接的第一接触插塞，设置在半导体层上的第二接触插塞和 电连接到第二区域，导电层电连接到第一接触插塞，导电层具有侧表面和底表面，以及绝缘层，设置在导电层和第二接触插塞之间，以使导电 层，所述绝缘层面向所述导电层的侧表面和所述底表面的一部分。

公开(公告)号：US07465988B2

公开(公告)日：2008-12-16

申请号：US11871876

申请日：2007-10-12

申请人： Sung-Sam Lee ,  Yong-Tae Kim ,  Mi-Youn Kim ,  Gyo-Young Jin ,  Dae-Won Ha ,  Yun-Gi Kim

发明人： Sung-Sam Lee ,  Yong-Tae Kim ,  Mi-Youn Kim ,  Gyo-Young Jin ,  Dae-Won Ha ,  Yun-Gi Kim

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/823437 ,  H01L21/823481

摘要： A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

摘要翻译： 提供能够抑制空穴迁移的半导体器件。 半导体器件包括在基本上垂直于字线延伸的第二方向的第一方向上延伸的虚拟区域。 此外，隔离层图案可以不在第二方向上切割伪区域。 因此，防止虚拟区域的倾斜和空隙迁移。 还提供了制造半导体器件的方法。

公开(公告)号：US07288823B2

公开(公告)日：2007-10-30

申请号：US11316307

申请日：2005-12-21

申请人： Jae-Mun Youn ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

发明人： Jae-Mun Youn ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7851 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

摘要： Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor includes forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.

摘要翻译： 提供双栅场效应晶体管及其制造方法。 制造双栅场效应晶体管的方法包括通过蚀刻硅衬底形成所需的散热片，通过绝缘材料如氮化硅掩蔽所得产物，通过使用氮化硅形成用于器件隔离的沟槽区域和STI膜 掩模，在除去硬掩模之后在翅片的两个表面上形成栅极氧化膜，并形成栅极线。 因此，当在没有突出的翅片形成的基板上形成厚的氧化硅膜时，通过在基板上施加高于阈值电压的电压，在氧化硅膜下形成不需要的通道。

公开(公告)号：US07056781B2

公开(公告)日：2006-06-06

申请号：US11014212

申请日：2004-12-15

申请人： Jae-Man Yoon ,  Gyo-Young Jin ,  Hee-Soo Kang ,  Dong-Gun Park

发明人： Jae-Man Yoon ,  Gyo-Young Jin ,  Hee-Soo Kang ,  Dong-Gun Park

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7854 ,  H01L29/78609

摘要： According to some embodiments, a fin type active region is formed under an exposure state of sidewalls on a semiconductor substrate. A gate insulation layer is formed on an upper part of the active region and on the sidewalls, and a device isolation film surrounds the active region to an upper height of the active region. The sidewalls are partially exposed by an opening part formed on the device isolation film. The opening part is filled with a conductive layer that partially covers the upper part of the active region, forming a gate electrode. Source and drain regions are on a portion of the active region where the gate electrode is not. The gate electrode may be easily separated and problems causable by etch by-product can be substantially reduced, and a leakage current of channel region and an electric field concentration onto an edge portion can be prevented.

摘要翻译： 根据一些实施例，在半导体衬底上的侧壁的曝光状态下形成鳍型有源区。 在有源区的上部和侧壁上形成栅极绝缘层，并且器件隔离膜将活性区域包围到有源区的上部高度。 侧壁由形成在器件隔离膜上的开口部分部分露出。 开口部分填充有部分覆盖有源区的上部的导电层，形成栅电极。 源极和漏极区域在栅电极不是的有源区域的一部分上。 可以容易地分离栅极电极，并且可以显着地减少由蚀刻副产物引起的问题，并且可以防止沟道区域的漏电流和电场集中在边缘部分上。

公开(公告)号：US20050255653A1

公开(公告)日：2005-11-17

申请号：US11166979

申请日：2005-06-24

申请人： Se-myeong Jang ,  Gyo-young Jin ,  Yong-chul Oh ,  Hyun-chang Kim

发明人： Se-myeong Jang ,  Gyo-young Jin ,  Yong-chul Oh ,  Hyun-chang Kim

IPC分类号： H01L21/8238 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/41783 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/823418 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628

摘要： Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is provided on the portion of the barrier layer spacer protruding from the sidewalls of the gate.

摘要翻译： 提供集成电路器件，其包括集成电路衬底和集成电路衬底上的栅极。 门有侧壁。 阻挡层间隔件设置在栅极的侧壁上。 阻挡层间隔物的一部分从栅极的侧壁突出，暴露出面向集成电路基板的阻挡层隔离物的下表面。 在从栅极的侧壁突出的阻挡层隔离物的部分上提供硅化物层。

公开(公告)号：US06875649B2

公开(公告)日：2005-04-05

申请号：US10686421

申请日：2003-10-15

申请人： Yong-chul Oh ,  Gyo-young Jin

发明人： Yong-chul Oh ,  Gyo-young Jin

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/331 ,  H01L29/00 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L21/76235

摘要： Integrated circuit devices including an isolation region are provided. The devices include an integrated circuit substrate and a trench in the integrated circuit substrate that defines an active region of the integrated circuit device. A silicon layer is provided on the integrated circuit substrate that extends over an edge of the trench and along an upper portion of a first sidewall of the trench. An insulating material is positioned adjacent the silicon layer that extends across some, or all, of the trench to define the isolation region. Methods of forming such integrated circuit devices are also provided.

摘要翻译： 提供了包括隔离区域的集成电路装置。 这些器件包括集成电路衬底和集成电路衬底中的限定集成电路器件的有源区的沟槽。 在集成电路基板上提供硅层，该沟槽在沟槽的边缘上并且沿着沟槽的第一侧壁的上部延伸。 绝缘材料位于硅层附近，该层延伸穿过沟槽的一些或全部以限定隔离区域。 还提供了形成这种集成电路器件的方法。

公开(公告)号：US08492832B2

公开(公告)日：2013-07-23

申请号：US13571805

申请日：2012-08-10

申请人： Ji-young Kim ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Yoo-sang Hwang ,  Sung-kwan Choi ,  Hyun-woo Chung

发明人： Ji-young Kim ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Yoo-sang Hwang ,  Sung-kwan Choi ,  Hyun-woo Chung

IPC分类号： H01L29/78

CPC分类号： H01L27/10876 ,  H01L27/10823 ,  H01L29/4236

摘要： A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation layer, a trench extending across the active region, a buried gate filling a part of the trench and including a base portion, a first extension portion, and a second extension portion extending along an inner wall of the trench, and having different heights at sides of the base portion, and a capping layer formed on the buried gate and filling the trench.

摘要翻译： 半导体器件包括半导体衬底，其包括由器件隔离层限定的有源区，横跨有源区延伸的沟槽，填充沟槽的一部分并包括基部的掩埋栅，第一延伸部和第二延伸部 沿着沟槽的内壁延伸的部分，并且在基部的侧面具有不同的高度，以及形成在掩埋栅极上并填充沟槽的覆盖层。

公开(公告)号：US07501668B2

公开(公告)日：2009-03-10

申请号：US11582926

申请日：2006-10-18

申请人： Se-Myeong Jang ,  Yong-chul Oh ,  Gyo-young Jin

发明人： Se-Myeong Jang ,  Yong-chul Oh ,  Gyo-young Jin

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L27/10855 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/105 ,  H01L27/10817 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device having a semiconductor substrate includes a gate structure on the semiconductor substrate. Source/drain regions are on opposite sides of the gate structure. A contact pad is on at least one of the source/drain region, and a silicide cap is on a surface of the contact pad opposite the respective source/drain region.

摘要翻译： 具有半导体衬底的集成电路器件包括半导体衬底上的栅极结构。 源极/漏极区位于栅极结构的相对侧。 接触焊盘位于源极/漏极区域中的至少一个上，并且硅化物帽位于与相应源极/漏极区域相对的接触焊盘的表面上。