公开(公告)号：US10776559B2

公开(公告)日：2020-09-15

申请号：US16383683

申请日：2019-04-15

Applicant: I-SHOU UNIVERSITY

Inventor： Yu-Jung Huang ,  Chung-Long Pan ,  Mei-Hui Guo

IPC: G06F30/398 ,  G06F11/263 ,  G06F11/22 ,  G06N20/00

Abstract: A defect detection method for a multilayer daisy chain structure, including: generating a plurality of physical models having a defect of at least one defect type based on the at least one defect type of a daisy chain structure; generating a group of training samples for each of the physical models; generating a classifier model by using a machine learning technique algorithm via scattering parameter values of a training set; measuring an error value by comparing scattering parameter values of a testing set with the classifier model, using the classifier model as a defect model of the defect type based on the error value, and determining that the multilayer daisy chain has a defect corresponding to the at least one defect type by comparing actual measurements of scattering parameter values.

公开(公告)号：US10303823B2

公开(公告)日：2019-05-28

申请号：US15604671

申请日：2017-05-25

Applicant: I-SHOU UNIVERSITY

Inventor： Yu-Jung Huang ,  Chung-Long Pan ,  Shih-Chun Lin ,  Mei-Hui Guo

IPC: G06F17/50 ,  G06N20/00

Abstract: A defect detection method for a 3D chip and a system using the same are provided. The method includes: generating a plurality of physical models having a defect of at least one defect type based on the at least one defect type of a 3D chip; generating a group of training samples for each of the physical models; generating a classifier model by using a machine learning technique algorithm via scattering parameter values of a training set; measuring an error value by comparing scattering parameter values of a testing set with the classifier model, using the classifier model as a defect model of the defect type based on the error value, and determining that a Through Silicon Via of a single die 3D chip or a stacked die 3D chip has a defect corresponding to the at least one defect type by comparing actual measurements of scattering parameter values.

公开(公告)号：US20180285493A1

公开(公告)日：2018-10-04

申请号：US15604671

申请日：2017-05-25

Applicant: I-SHOU UNIVERSITY

Inventor： Yu-Jung Huang ,  Chung-Long Pan ,  Shih-Chun Lin ,  Mei-Hui Guo

IPC: G06F17/50 ,  G06N99/00

CPC classification number: G06F17/5009 ,  G06F17/5081 ,  G06N99/005

Abstract: A defect detection method for a 3D chip and a system using the same are provided. The method includes: generating a plurality of physical models having a defect of at least one defect type based on the at least one defect type of a 3D chip; generating a group of training samples for each of the physical models; generating a classifier model by using a machine learning technique algorithm via scattering parameter values of a training set; measuring an error value by comparing scattering parameter values of a testing set with the classifier model, using the classifier model as a defect model of the defect type based on the error value, and determining that a Through Silicon Via of a single die 3D chip or a stacked die 3D chip has a defect corresponding to the at least one defect type by comparing actual measurements of scattering parameter values.

公开(公告)号：US10063282B1

公开(公告)日：2018-08-28

申请号：US15657209

申请日：2017-07-24

Applicant: I-SHOU UNIVERSITY

Inventor： Yu-Jung Huang ,  Mei-Hui Guo

IPC: H04B5/00

CPC classification number: H04B5/0012 ,  H04B5/0031

Abstract: A chip-to-chip signal transmission system including a first unit set and a second unit set arranged in a first direction is provided. The first unit set and the second unit are configured to perform the signal transmission between a first chip and a second chip. There is a shift between the first unit set and the second unit set in a second direction such that the first unit set and the second unit set are shifted in the second direction and an overlapping region is formed. By adjusting the size of the overlapping region, the signal noise and the signal attenuation due to the misalignment between the first chip and the second chip or the electromagnetic interference of the adjacent signals are reduced and the signal transmission quality is thus improved. Furthermore, a method for arranging chips is also provided.

公开(公告)号：US11748545B2

公开(公告)日：2023-09-05

申请号：US17458598

申请日：2021-08-27

Applicant: I-SHOU UNIVERSITY

Inventor： Yu-Jung Huang ,  Mong-Na Lo Huang ,  Tzu-Lun Yuan ,  Mei-Hui Guo

IPC: G06F30/00 ,  G06F30/392 ,  H04B17/391 ,  H01L25/065

CPC classification number: G06F30/392 ,  H04B17/391 ,  H01L25/0657 ,  H01L2225/06531

Abstract: A method and an electronic device for configuring signal pads between three-dimensional stacked chips are provided. The method includes: obtaining a plurality of frequency response curves corresponding to a plurality of parameter sets; obtaining an operating frequency; selecting a selected frequency response curve from the plurality of frequency response curves according to the operating frequency, where the selected frequency response curve corresponds to a selected parameter set among the plurality of parameter sets; generating, according to the selected parameter set, a signal pad configuration for configuring a first signal pad and a second signal pad on a surface of a chip; and outputting the signal pad configuration.

公开(公告)号：US20230038144A1

公开(公告)日：2023-02-09

申请号：US17458598

申请日：2021-08-27

Applicant: I-SHOU UNIVERSITY

Inventor： Yu-Jung Huang ,  Mong-Na Lo Huang ,  Tzu-Lun Yuan ,  Mei-Hui Guo

IPC: G06F30/392 ,  H04B17/391

Abstract: A method and an electronic device for configuring signal pads between three-dimensional stacked chips are provided. The method includes: obtaining a plurality of frequency response curves corresponding to a plurality of parameter sets; obtaining an operating frequency; selecting a selected frequency response curve from the plurality of frequency response curves according to the operating frequency, where the selected frequency response curve corresponds to a selected parameter set among the plurality of parameter sets; generating, according to the selected parameter set, a signal pad configuration for configuring a first signal pad and a second signal pad on a surface of a chip; and outputting the signal pad configuration.

公开(公告)号：US20190236240A1

公开(公告)日：2019-08-01

申请号：US16383683

申请日：2019-04-15

Applicant: I-SHOU UNIVERSITY

Inventor： Yu-Jung Huang ,  Chung-Long Pan ,  Mei-Hui Guo

IPC: G06F17/50 ,  G06N20/00 ,  G06F11/22 ,  G06F11/263

Abstract: A defect detection method for a multilayer daisy chain structure, including: generating a plurality of physical models having a defect of at least one defect type based on the at least one defect type of a daisy chain structure; generating a group of training samples for each of the physical models; generating a classifier model by using a machine learning technique algorithm via scattering parameter values of a training set; measuring an error value by comparing scattering parameter values of a testing set with the classifier model, using the classifier model as a defect model of the defect type based on the error value, and determining that the multilayer daisy chain has a defect corresponding to the at least one defect type by comparing actual measurements of scattering parameter values.