公开(公告)号：US10439036B2

公开(公告)日：2019-10-08

申请号：US15374886

申请日：2016-12-09

Applicant: IMEC VZW

Inventor： Alessio Spessot ,  An De Keersgieter ,  Naoto Horiguchi

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/265 ,  H01L29/49

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices such as metal-oxide-semiconductor (MOS) transistor devices. In one aspect, a transistor device comprises a channel region in a substrate partially delimited by a source and a drain junction at a main surface of the substrate. A first dielectric layer stack is arranged on the channel region, such that an orthogonal projection of the first dielectric layer stack on the main surface defining a first area is between and does not overlap the junctions and. A second dielectric layer stack is formed laterally adjacent to and in contact with the first dielectric layer stack, such that an orthogonal projection of the second dielectric layer stack overlaps the junction and defines a second area. A metal gate layer is formed on the first and second dielectric layer stacks, where an orthogonal projection of the metal gate layer on the main surface overlaps the first area and the second area. The first dielectric layer stack has a larger capacitance than the second dielectric layer stack.

公开(公告)号：US20170170289A1

公开(公告)日：2017-06-15

申请号：US15374886

申请日：2016-12-09

Applicant: IMEC VZW

Inventor： Alessio Spessot ,  An De Keersgieter ,  Naoto Horiguchi

IPC: H01L29/51 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/512 ,  H01L21/265 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices such as metal-oxide-semiconductor (MOS) transistor devices. In one aspect, a transistor device comprises a channel region in a substrate partially delimited by a source and a drain junction at a main surface of the substrate. A first dielectric layer stack is arranged on the channel region, such that an orthogonal projection of the first dielectric layer stack on the main surface defining a first area is between and does not overlap the junctions and. A second dielectric layer stack is formed laterally adjacent to and in contact with the first dielectric layer stack, such that an orthogonal projection of the second dielectric layer stack overlaps the junction and defines a second area. A metal gate layer is formed on the first and second dielectric layer stacks, where an orthogonal projection of the metal gate layer on the main surface overlaps the first area and the second area. The first dielectric layer stack has a larger capacitance than the second dielectric layer stack

公开(公告)号：US20240178051A1

公开(公告)日：2024-05-30

申请号：US18524355

申请日：2023-11-30

Applicant: IMEC VZW

Inventor： Anabela Veloso ,  Rongmei Chen ,  An De Keersgieter ,  Geert Eneman ,  Philippe Matagne

IPC: H01L21/74 ,  H01L21/768

CPC classification number: H01L21/743 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76879 ,  H01L21/823431

Abstract: A method includes: forming a structure on a frontside of a substrate, the structure including a first and a second source/drain body located in a first and a second source/drain region, respectively, and a channel body including a channel layer extending between the first and second source/drain bodies; forming a trench beside the first source/drain region by etching the substrate such that a lower portion of the trench undercuts the first source/drain region; forming a liner on the trench; forming an opening in the liner underneath the first source/drain region; and forming a dummy interconnect in the trench; where the method further includes exposing the dummy interconnect from a backside of the substrate; removing the dummy interconnect selectively to the liner; and forming a buried interconnect of a conductive material in the trench, where the buried interconnect is connected to the first source/drain body via the opening in the liner.

公开(公告)号：US20210336057A1

公开(公告)日：2021-10-28

申请号：US17241318

申请日：2021-04-27

Applicant: IMEC VZW

Inventor： Geert Eneman ,  Basoene Briggs ,  An De Keersgieter ,  Anabela Veloso ,  Paola Favia

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor structure comprises a semiconductor substrate having a top layer and one or more semiconductor monocrystalline nanostructures. Each nanostructure has a first and a second extremity defining an axis parallel to the top surface of the semiconductor substrate and separated therefrom by a distance, and a source structure epitaxially grown on the first extremity and a drain structure epitaxially grown on the second extremity. The source and drain structures are made of a p-doped (or alternatively n-doped) semiconductor monocrystalline material having a smaller (or alternatively larger) unstrained lattice constant than the unstrained lattice constant of the semiconductor monocrystalline material making the semiconductor monocrystalline nanostructure on which they are grown, thereby creating compressive (or alternatively tensile) strain in that semiconductor monocrystalline nanostructure.