公开(公告)号：US10811315B2

公开(公告)日：2020-10-20

申请号：US16456833

申请日：2019-06-28

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Stefaan Van Huylenbroeck ,  Geert Van der Plas

IPC: H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L25/065 ,  H01L23/538 ,  H01L23/48 ,  H01L23/00

Abstract: A method of producing a through semiconductor via (TSV) connection is disclosed. In one aspect, an opening of the TSV is produced for contacting a first semiconductor die bonded to a second die or to a temporary carrier. The first die includes fin-shaped devices in the front end of line of the die. Etching of the TSV opening does not end on a metal pad, but the opening is etched until reaching a well that is formed of material of a first doping type and formed in the first die amid semiconductor material of a second doping type opposite the first. After filling the TSV opening with a conductive material, the TSV connects to a conductor of an intermediate metallization (IM) of the first die through at least one fin extending from the well and connected to the conductor. A package of dies comprising at least one TSV produced by the above method is also disclosed.

公开(公告)号：US20200006142A1

公开(公告)日：2020-01-02

申请号：US16456833

申请日：2019-06-28

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Stefaan Van Huylenbroeck ,  Geert Van der Plas

IPC: H01L21/768 ,  H01L21/8238 ,  H01L23/48 ,  H01L27/092 ,  H01L23/00

Abstract: A method of producing a through semiconductor via (TSV) connection is disclosed. In one aspect, an opening of the TSV is produced for contacting a first semiconductor die bonded to a second die or to a temporary carrier. The first die includes fin-shaped devices in the front end of line of the die. Etching of the TSV opening does not end on a metal pad, but the opening is etched until reaching a well that is formed of material of a first doping type and formed in the first die amid semiconductor material of a second doping type opposite the first. After filling the TSV opening with a conductive material, the TSV connects to a conductor of an intermediate metallization (IM) of the first die through at least one fin extending from the well and connected to the conductor. A package of dies comprising at least one TSV produced by the above method is also disclosed.

公开(公告)号：US10607901B2

公开(公告)日：2020-03-31

申请号：US16121369

申请日：2018-09-04

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Geert Van der Plas ,  Stefaan Van Huylenbroeck

IPC: H01L21/66 ,  G01L1/18 ,  G01L1/22 ,  G01L1/16 ,  G01L5/161 ,  H01L21/265

Abstract: An example embodiment may include a sensor for monitoring and/or measuring stress in a semiconductor component. The component may include a substrate formed of a semiconductor material. The substrate may include a planar main surface. The sensor may include at least one slanted surface of the substrate material, the slanted surface being defined by an oblique inclination angle with respect to the main surface of the substrate. The sensor may also include at least one straight resistive path extending on at least part of the slanted surface and a plurality of contacts and terminals for accessing the at least one resistive path. The contacts and terminals may allow for the measurement of an electrical resistance of the resistive path and an assessment of a shear stress in a plane that is not parallel to the main surface of the substrate.

公开(公告)号：US20190181133A1

公开(公告)日：2019-06-13

申请号：US16215492

申请日：2018-12-10

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Geert Van der Plas ,  Stefaan Van Huylenbroeck

IPC: H01L27/02 ,  H01L23/60 ,  H01L23/48 ,  H01L21/3065 ,  H01L21/768

CPC classification number: H01L27/0259 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/60 ,  H01L27/0292

Abstract: The disclosed technology relates to a semiconductor integrated circuit that comprises a semiconductor device which has a port to be protected from Plasma-Induced Damage due to electric charge that may accumulate at the port during a plasma-processing step, and a protection circuit that is provided to the integrated circuit. In one aspect, the protection circuit comprises a discharge path, a control terminal, and a plasma pick-up antenna connected to the control terminal. The protection circuit further comprises a bipolar transistor which has a base connected to the control terminal. Such protection circuit is much more efficient in allowing charge transfer from the device port to a reference voltage terminal.

公开(公告)号：US20180068984A1

公开(公告)日：2018-03-08

申请号：US15697285

申请日：2017-09-06

Applicant: IMEC VZW

Inventor： Eric Beyne ,  Joeri De Vos ,  Stefaan Van Huylenbroeck

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/3065 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/08 ,  H01L24/89 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80125 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/14

Abstract: A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. At least the upper substrate is provided prior to bonding with a cavity in its bonding surface. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly and an aggregate opening is formed including the TSV opening and the cavity. After the formation of an isolation liner on at least part of the sidewalls of the aggregate opening (that is, at least on the part where the liner isolates the aggregate opening from semiconductor material), a TSV interconnection plug is produced in the aggregate opening.

公开(公告)号：US10825806B2

公开(公告)日：2020-11-03

申请号：US16215492

申请日：2018-12-10

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Geert Van der Plas ,  Stefaan Van Huylenbroeck

IPC: H01L27/02 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/60

Abstract: The disclosed technology relates to a semiconductor integrated circuit that comprises a semiconductor device which has a port to be protected from Plasma-Induced Damage due to electric charge that may accumulate at the port during a plasma-processing step, and a protection circuit that is provided to the integrated circuit. In one aspect, the protection circuit comprises a discharge path, a control terminal, and a plasma pick-up antenna connected to the control terminal. The protection circuit further comprises a bipolar transistor which has a base connected to the control terminal. Such protection circuit is much more efficient in allowing charge transfer from the device port to a reference voltage terminal.

公开(公告)号：US20190074231A1

公开(公告)日：2019-03-07

申请号：US16121369

申请日：2018-09-04

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Geert Van der Plas ,  Stefaan Van Huylenbroeck

IPC: H01L21/66 ,  H01L21/265 ,  G01L1/18

Abstract: An example embodiment may include a sensor for monitoring and/or measuring stress in a semiconductor component. The component may include a substrate formed of a semiconductor material. The substrate may include a planar main surface. The sensor may include at least one slanted surface of the substrate material, the slanted surface being defined by an oblique inclination angle with respect to the main surface of the substrate. The sensor may also include at least one straight resistive path extending on at least part of the slanted surface and a plurality of contacts and terminals for accessing the at least one resistive path. The contacts and terminals may allow for the measurement of an electrical resistance of the resistive path and an assessment of a shear stress in a plane that is not parallel to the main surface of the substrate.

公开(公告)号：US10170450B2

公开(公告)日：2019-01-01

申请号：US15697285

申请日：2017-09-06

Applicant: IMEC VZW

Inventor： Eric Beyne ,  Joeri De Vos ,  Stefaan Van Huylenbroeck

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48 ,  H01L21/3065

Abstract: A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. At least the upper substrate is provided prior to bonding with a cavity in its bonding surface. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly and an aggregate opening is formed including the TSV opening and the cavity. After the formation of an isolation liner on at least part of the sidewalls of the aggregate opening (that is, at least on the part where the liner isolates the aggregate opening from semiconductor material), a TSV interconnection plug is produced in the aggregate opening.