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    Circuit Cell for a Memory Device or Logic Device
    2.
    发明申请
    Circuit Cell for a Memory Device or Logic Device 审中-公开

    公开(公告)号：US20200211642A1

    公开(公告)日：2020-07-02

    申请号：US16727653

    申请日：2019-12-26

    Applicant: IMEC VZW

    Inventor： Trong Huynh Bao ,  Sushil Sakhare

    IPC: G11C13/00 ,  G11C14/00

    Abstract: A circuit cell for a memory device or a logic device comprises: (i) first and a second logic gates having respective output nodes; and (ii) first and second memory units, each comprising (a) first and second terminals and (b) a resistive memory element and a bipolar selector connected in series between the first and second terminals, wherein the first terminals of the first and second memory units are connected to the output nodes of the first and second logic gates, respectively, wherein the resistive memory elements are configured to be switchable between first and second resistance states, and wherein in response to a switching current and the bipolar selectors are configured to be conducting in response to an absolute value of a voltage difference across the bipolar selectors exceeding a threshold voltage of the bipolar selectors and non-conducting in response to the absolute value being lower than the threshold.

    Multibit neural network
    3.
    发明授权
    Multibit neural network 有权

    公开(公告)号：US11645503B2

    公开(公告)日：2023-05-09

    申请号：US16723131

    申请日：2019-12-20

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

    Inventor： Mohit Gupta ,  Bharani Chakravarthy Chava ,  Wim Dehaene ,  Sushil Sakhare

    IPC: G06N3/063 ,  G06F7/544 ,  G06N3/04 ,  G11C11/54

    CPC classification number: G06N3/063 ,  G06F7/5443 ,  G06N3/04 ,  G11C11/54

    Abstract: A circuit is provided. The circuit includes a sampling circuit connectable to a multibit memory array and that samples a voltage across a sampling capacitor, a capacitance network including a plurality of capacitors and switching elements such that the capacitance network has a capacitance that depends on the configuration of the switching elements, and a buffering circuit configured to charge the capacitance of the capacitance network based on the voltage across the sampling capacitor. The circuit is configured to operate the capacitance network in a first state and a second state, wherein the capacitance in the states depends on an input value to the circuit. The circuit is also configured to charge the capacitance network in the first state and to allow the charge to redistribute within the capacitance network when it changes from the first to the second state. A system and method including such circuits are also provided.

    Resistance change memory device configured for state evaluation based on reference cells
    5.
    发明授权
    Resistance change memory device configured for state evaluation based on reference cells 有权

    公开(公告)号：US10170182B2

    公开(公告)日：2019-01-01

    申请号：US15458874

    申请日：2017-03-14

    Applicant: IMEC VZW

    Inventor： Sushil Sakhare

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16 ,  G11C13/04

    Abstract: The disclosed technology generally relates to memory devices and more particularly to memory devices based on resistance change, and to systems and methods for evaluating states of memory cells of the memory devices. In one aspect, a memory device includes a plurality of memory cells arranged in an array, where each memory cell comprises a memory element configured to be switched between at least two resistance states. The memory device additionally includes a plurality of word lines and a plurality of bit lines crossing each other, where each of the memory cells is formed at a crossing between one of the word lines and one of the bit lines. In the memory device, the memory cells are configured to be connected to a source line. Additionally, each bit line has a bit line capacitance and is configured to store a charge associated with a state of a selected memory element. Additionally, at least two memory cells electrically connected between one of the word lines and at least two different bit lines are configured as reference cells, where one of the reference cells is in a high resistance state and the other of the reference cells is in a low resistance state. Furthermore, the at least two different bit lines electrically connected to the reference cells are interconnected by an equalizing switch configured to equalize charges associated with bit line capacitances of the at least two bit lines.

    Circuit cell for a memory device or logic device
    7.
    发明授权
    Circuit cell for a memory device or logic device 有权

    公开(公告)号：US11087837B2

    公开(公告)日：2021-08-10

    申请号：US16727653

    申请日：2019-12-26

    Applicant: IMEC VZW

    Inventor： Trong Huynh Bao ,  Sushil Sakhare

    IPC: G11C8/10 ,  G11C17/02 ,  G11C13/00 ,  G11C14/00

    Abstract: A circuit cell for a memory device or a logic device comprises: (i) first and a second logic gates having respective output nodes; and (ii) first and second memory units, each comprising (a) first and second terminals and (b) a resistive memory element and a bipolar selector connected in series between the first and second terminals, wherein the first terminals of the first and second memory units are connected to the output nodes of the first and second logic gates, respectively, wherein the resistive memory elements are configured to be switchable between first and second resistance states, and wherein in response to a switching current and the bipolar selectors are configured to be conducting in response to an absolute value of a voltage difference across the bipolar selectors exceeding a threshold voltage of the bipolar selectors and non-conducting in response to the absolute value being lower than the threshold.

    Multibit Neural Network
    8.
    发明申请
    Multibit Neural Network 审中-公开

    公开(公告)号：US20200210822A1

    公开(公告)日：2020-07-02

    申请号：US16723131

    申请日：2019-12-20

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

    Inventor： Mohit Gupta ,  Bharani Chakravarthy Chava ,  Wim Dehaene ,  Sushil Sakhare

    IPC: G06N3/063 ,  G11C11/54 ,  G06N3/04 ,  G06F7/544

    Abstract: A circuit is provided. The circuit includes a sampling circuit connectable to a multibit memory array and that samples a voltage across a sampling capacitor, a capacitance network including a plurality of capacitors and switching elements such that the capacitance network has a capacitance that depends on the configuration of the switching elements, and a buffering circuit configured to charge the capacitance of the capacitance network based on the voltage across the sampling capacitor. The circuit is configured to operate the capacitance network in a first state and a second state, wherein the capacitance in the states depends on an input value to the circuit. The circuit is also configured to charge the capacitance network in the first state and to allow the charge to redistribute within the capacitance network when it changes from the first to the second state. A system and method including such circuits are also provided.

    MAGNETIC TUNNEL JUNCTION UNIT AND A MEMORY DEVICE
    9.
    发明申请
    MAGNETIC TUNNEL JUNCTION UNIT AND A MEMORY DEVICE 审中-公开

    公开(公告)号：US20200185016A1

    公开(公告)日：2020-06-11

    申请号：US16705937

    申请日：2019-12-06

    Applicant: IMEC VZW ,  VRIJE UNIVERSITEIT BRUSSEL

    Inventor： Sushil Sakhare ,  Manu Komalan Perumkunnil ,  Johan Swerts ,  Gouri Sankar Kar ,  Trong Huynh Bao

    IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

    Abstract: According to an example embodiment an MTJ unit is provided. The MTJ unit includes: a first MTJ comprising a first free layer, a first tunnel barrier layer and a first reference layer. The first MTJ is switchable between a parallel state and an anti-parallel state through spin-torque transfer (STT). The MTJ unit comprises a second MTJ arranged above the first MTJ and comprising, a second reference layer, a second tunnel barrier layer and a second free layer. The second MTJ is switchable between a parallel state and an anti-parallel state through STT. The MTJ unit comprises a pinning layer arranged between the first reference layer and the second reference layer and configured to fix a magnetization direction of the first reference layer and the second reference layer.

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