公开(公告)号：US20200050112A1

公开(公告)日：2020-02-13

申请号：US16659034

申请日：2019-10-21

Applicant: IMEC VZW

Inventor： Christopher Ausschnitt ,  Vincent Truffert

IPC: G03F7/20

Abstract: Examples herein are related to a method and apparatus for determining dimensions of features in a patterned layer of a chip produced on a semiconductor production wafer. The production of the patterned layer includes a lithography step and an etching step, where the lithographic mask applied for producing the patterned layer is provided with one or more asymmetric marks. The position of printed and etched mark features is sensitive to lithographic and etch parameters. Changes in these positions are measured by overlay measurements, i.e. the measurement of the change in position of one mark relative to another. The obtained ‘pseudo’ overlay data are fitted to a parametric model, while characteristic feature dimensions are measured on a test wafer. The inverted model allows determination of feature dimensions on a production wafer. Application of the method on two different layers allows determination of edge placement errors between features of the two layers.

公开(公告)号：US10481504B2

公开(公告)日：2019-11-19

申请号：US16308363

申请日：2017-06-09

Applicant: IMEC VZW

Inventor： Christopher Ausschnitt ,  Vincent Truffert

IPC: G06F17/50 ,  G03F7/20

Abstract: Examples herein are related to a method and apparatus for determining dimensions of features in a patterned layer of a chip produced on a semiconductor production wafer. The production of the patterned layer includes a lithography step and an etching step, where the lithographic mask applied for producing the patterned layer is provided with one or more asymmetric marks. The position of printed and etched mark features is sensitive to lithographic and etch parameters. Changes in these positions are measured by overlay measurements, i.e. the measurement of the change in position of one mark relative to another. The obtained ‘pseudo’ overlay data are fitted to a parametric model, while characteristic feature dimensions are measured on a test wafer. The inverted model allows determination of feature dimensions on a production wafer. Application of the method on two different layers allows determination of edge placement errors between features of the two layers.

公开(公告)号：US10824081B2

公开(公告)日：2020-11-03

申请号：US16842526

申请日：2020-04-07

Applicant: IMEC VZW

Inventor： Christopher Ausschnitt ,  Vincent Truffert

IPC: G03F7/20

Abstract: A method and apparatus is disclosed for monitoring critical dimensions in a pattern of 1-dimensional and/or 2-dimensional features, produced on a substrate in a process step that is part of or related to a manufacturing process for producing a semiconductor device, the process step being performed in accordance with a predefined pattern design, wherein one or more metrology targets (1) are added to the pattern design. The targets comprise one or more versions of an asymmetric metrology mark, each version of the mark comprising a uniform portion (2) and a periodic portion (3), the latter comprising a regular array of parallel line-shaped features or an array of 2-dimensional features. The design width of the features is situated in a range situated around a nominal design width w0. A position-related parameter S is defined that is essentially proportional to the design widths in the range. Determination of the shift δS of the S parameter with respect to a pre-defined process operating point, allows to assess the critical dimension of the features produced by the process step.

公开(公告)号：US09874821B2

公开(公告)日：2018-01-23

申请号：US15134616

申请日：2016-04-21

Applicant: IMEC VZW

Inventor： Sandip Halder ,  Dieter Van Den Heuvel ,  Vincent Truffert ,  Philippe Leray

IPC: G01N21/00 ,  G03F7/20 ,  G03F1/84 ,  G01N21/88 ,  G01N21/956

CPC classification number: G03F7/7065 ,  G01N21/8851 ,  G01N21/95607 ,  G01N2021/8854 ,  G01N2021/95676 ,  G03F1/84 ,  G03F7/70441 ,  G03F7/70625 ,  G03F7/70641

Abstract: The present disclosure is related to a method for detecting and ranking hotspots in a lithographic mask used for printing a pattern on a substrate. According to example embodiments, the ranking is based on defect detection on a modulated focus wafer or a modulated dose wafer, where the actual de-focus or dose value at defect locations is taken into account, in addition to a de-focus or dose setting applied to a lithographic tool when a mask pattern is printed on the wafer. Additionally or alternatively, lithographic parameters other than the de-focus or dose can be used as a basis for the ranking method.

公开(公告)号：US20200233317A1

公开(公告)日：2020-07-23

申请号：US16842526

申请日：2020-04-07

Applicant: IMEC VZW

Inventor： Christopher Ausschnitt ,  Vincent Truffert

IPC: G03F7/20

Abstract: A method and apparatus is disclosed for monitoring critical dimensions in a pattern of 1-dimensional and/or 2-dimensional features, produced on a substrate in a process step that is part of or related to a manufacturing process for producing a semiconductor device, the process step being performed in accordance with a predefined pattern design, wherein one or more metrology targets (1) are added to the pattern design. The targets comprise one or more versions of an asymmetric metrology mark, each version of the mark comprising a uniform portion (2) and a periodic portion (3), the latter comprising a regular array of parallel line-shaped features or an array of 2-dimensional features. The design width of the features is situated in a range situated around a nominal design width w0. A position-related parameter S is defined that is essentially proportional to the design widths in the range. Determination of the shift δS of the S parameter with respect to a pre-defined process operating point, allows to assess the critical dimension of the features produced by the process step.

公开(公告)号：US10656535B2

公开(公告)日：2020-05-19

申请号：US15938002

申请日：2018-03-28

Applicant: IMEC VZW

Inventor： Christopher Ausschnitt ,  Vincent Truffert

IPC: G03F7/20

Abstract: A method and apparatus is disclosed for monitoring critical dimensions in a pattern of 1-dimensional and/or 2-dimensional features, produced on a substrate in a process step that is part of or related to a manufacturing process for producing a semiconductor device, the process step being performed in accordance with a predefined pattern design, wherein one or more metrology targets (1) are added to the pattern design. The targets comprise one or more versions of an asymmetric metrology mark, each version of the mark comprising a uniform portion (2) and a periodic portion (3), the latter comprising a regular array of parallel line-shaped features or an array of 2-dimensional features. The design width of the features is situated in a range situated around a nominal design width w0. A position-related parameter S is defined that is essentially proportional to the design widths in the range. Determination of the shift δS of the S parameter with respect to a pre-defined process operating point, allows to assess the critical dimension of the features produced by the process step.

公开(公告)号：US20190137881A1

公开(公告)日：2019-05-09

申请号：US16308363

申请日：2017-06-09

Applicant: IMEC VZW

Inventor： Christopher Ausschnitt ,  Vincent Truffert

IPC: G03F7/20

CPC classification number: G03F7/705 ,  G03F7/70616 ,  G03F7/70625 ,  G03F7/70633

Abstract: Examples herein are related to a method and apparatus for determining dimensions of features in a patterned layer of a chip produced on a semiconductor production wafer. The production of the patterned layer includes a lithography step and an etching step, where the lithographic mask applied for producing the patterned layer is provided with one or more asymmetric marks. The position of printed and etched mark features is sensitive to lithographic and etch parameters. Changes in these positions are measured by overlay measurements, i.e. the measurement of the change in position of one mark relative to another. The obtained ‘pseudo’ overlay data are fitted to a parametric model, while characteristic feature dimensions are measured on a test wafer. The inverted model allows determination of feature dimensions on a production wafer. Application of the method on two different layers allows determination of edge placement errors between features of the two layers.

公开(公告)号：US20180284624A1

公开(公告)日：2018-10-04

申请号：US15938002

申请日：2018-03-28

Applicant: IMEC VZW

Inventor： Christopher Ausschnitt ,  Vincent Truffert

IPC: G03F7/20 ,  G01B11/22 ,  G01B11/30

Abstract: A method and apparatus is disclosed for monitoring critical dimensions in a pattern of 1-dimensional and/or 2-dimensional features, produced on a substrate in a process step that is part of or related to a manufacturing process for producing a semiconductor device, the process step being performed in accordance with a predefined pattern design, wherein one or more metrology targets (1) are added to the pattern design. The targets comprise one or more versions of an asymmetric metrology mark, each version of the mark comprising a uniform portion (2) and a periodic portion (3), the latter comprising a regular array of parallel line-shaped features or an array of 2-dimensional features. The design width of the features is situated in a range situated around a nominal design width w0. A position-related parameter S is defined that is essentially proportional to the design widths in the range. Determination of the shift δS of the S parameter with respect to a pre-defined process operating point, allows to assess the critical dimension of the features produced by the process step.

公开(公告)号：US20160313647A1

公开(公告)日：2016-10-27

申请号：US15134616

申请日：2016-04-21

Applicant: IMEC VZW

Inventor： Sandip Halder ,  Dieter Van Den Heuvel ,  Vincent Truffert ,  Philippe Leray

IPC: G03F7/20 ,  G01N21/88 ,  G01N21/956

CPC classification number: G03F7/7065 ,  G01N21/8851 ,  G01N21/95607 ,  G01N2021/8854 ,  G01N2021/95676 ,  G03F1/84 ,  G03F7/70441 ,  G03F7/70625 ,  G03F7/70641

Abstract: The present disclosure is related to a method for detecting and ranking hotspots in a lithographic mask used for printing a pattern on a substrate. According to example embodiments, the ranking is based on defect detection on a modulated focus wafer or a modulated dose wafer, where the actual de-focus or dose value at defect locations is taken into account, in addition to a de-focus or dose setting applied to a lithographic tool when a mask pattern is printed on the wafer. Additionally or alternatively, lithographic parameters other than the de-focus or dose can be used as a basis for the ranking method.

Abstract translation: 本公开涉及用于在用于在基板上印刷图案的光刻掩模中检测和排列热点的方法。 根据示例实施例，排序基于调制聚焦晶片或调制剂量晶片上的缺陷检测，其中除了去焦点或剂量设置之外还考虑了缺陷位置处的实际去焦点或剂量值 当将掩模图案印刷在晶片上时应用于光刻工具。 附加地或替代地，除去焦点或剂量之外的光刻参数可以用作排序方法的基础。