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公开(公告)号：US11201093B2
公开(公告)日：2021-12-14
申请号：US16836653
申请日：2020-03-31
Applicant: IMEC vzw
Inventor： Anabela Veloso , Trong Huynh Bao , Julien Ryckaert , Raf Appeltans
IPC: H01L21/8234 , H01L27/088
Abstract: A method of fabricating a semiconductor device is disclosed. In one aspect, the method includes forming, in a vertical channel field-effect transistor (FET) device region, a vertical channel FET device including a first semiconductor structure including a lower source/drain portion, an upper source/drain portion, a first channel portion extending vertically and intermediate the source/drain portions and a gate structure extending along the channel portion and, in a horizontal channel FET device region, a horizontal channel FET device comprising a second semiconductor structure including a first source/drain portion, a second source/drain portion, a second channel portion extending horizontally and intermediate the source/drain portions, and a gate structure extending across the channel portion.
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公开(公告)号：US11217488B2
公开(公告)日：2022-01-04
申请号：US16835786
申请日：2020-03-31
Applicant: IMEC vzw
Inventor： Anabela Veloso , Trong Huynh Bao , Raf Appeltans
IPC: H01L21/8234 , H01L21/311
Abstract: The disclosed technology generally relates to semiconductor devices and methods of forming the same. In one aspect, a method of forming a semiconductor device having vertical channel field-effect transistor (FET) devices comprises forming on a substrate, a plurality of semiconductor structures protruding vertically from a lower source/drain semiconductor layer of the substrate. The semiconductor structures can be arranged in an array having a plurality of rows and columns. The method can include etching metal line trenches between at least a subset of the rows and forming metal lines in the metal line trenches to contact the lower source/drain layer. The method can also include forming gate structures at least partly enclosing semiconductor structure channel portions located above the lower source/drain layer and forming upper source/drain metal contacts on semiconductor structure upper source/drain portions located above the channel portions.
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公开(公告)号：US20200312726A1
公开(公告)日：2020-10-01
申请号：US16836653
申请日：2020-03-31
Applicant: IMEC vzw
Inventor： Anabela Veloso , Trong Huynh Bao , Julien Ryckaert , Raf Appeltans
IPC: H01L21/8234 , H01L27/088
Abstract: A method of fabricating a semiconductor device is disclosed. In one aspect, the method includes forming, in a vertical channel field-effect transistor (FET) device region, a vertical channel FET device including a first semiconductor structure including a lower source/drain portion, an upper source/drain portion, a first channel portion extending vertically and intermediate the source/drain portions and a gate structure extending along the channel portion and, in a horizontal channel FET device region, a horizontal channel FET device comprising a second semiconductor structure including a first source/drain portion, a second source/drain portion, a second channel portion extending horizontally and intermediate the source/drain portions, and a gate structure extending across the channel portion.
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Patent Agency Ranking
公开(公告)号：US10797224B2
公开(公告)日：2020-10-06
申请号：US15904189
申请日：2018-02-23
Applicant: IMEC VZW , Katholieke Universiteit Leuven
Inventor： Praveen Raghavan , Davide Francesco Crotti , Raf Appeltans
Abstract: The disclosed technology generally relates to magnetoresistive devices, and more particularly to a magnetic tunnel junction (MTJ) device formed in an interconnection structure, and to a method of integrating the (MTJ) device in the interconnection structure. According to an aspect, a device includes a first interconnection level including a first dielectric layer and a first set of conductive paths arranged in the first dielectric layer, a second interconnection level arranged on the first connection level and including a second dielectric layer and a second set of conductive paths arranged in the second dielectric layer, and a third interconnection level arranged on the second interconnection level and including a third dielectric layer and a third set of conductive paths arranged in the third dielectric layer. The device additionally includes a magnetic tunnel junction (MTJ) device including a bottom layer, a top layer and an MTJ structure arranged between the bottom layer and the top layer, wherein the bottom layer is connected to a bottom layer contact portion of the first set of conductive paths and the top layer is connected to a top layer contact portion of the second or third set of conductive paths. The device further includes a multi-level via extending through the second dielectric layer and the third dielectric layer, between a first via contact portion of the first set of conductive paths and a second via contact portion of the third set of conductive paths, wherein a height of the MTJ device corresponds to, or-is less than, a height of the multi-level via, e.g., wherein the height of the MTJ device corresponds to or is less than a height of the second interconnection level.
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公开(公告)号：US20200312725A1
公开(公告)日：2020-10-01
申请号：US16836478
申请日：2020-03-31
Applicant: IMEC vzw
Inventor： Anabela Veloso , Trong Huynh Bao , Julien Ryckaert , Raf Appeltans
IPC: H01L21/8234
Abstract: The disclosed technology relates to methods of fabricating field-effect transistors having channels extending in horizontal and vertical directions. According to an aspect, a method comprises: providing a semiconductor substrate comprising: in a vertical channel field-effect transistor (FET) device region, a first layer structure comprising a lower semiconductor layer, an intermediate semiconductor layer above the lower semiconductor layer and an upper semiconductor layer above the intermediate semiconductor layer, and, in a horizontal channel FET device region, a second layer structure comprising at least one semiconductor layer, wherein the first layer structure and the second layer structure have different compositions and wherein a surface of the substrate in the vertical channel FET device region is coplanar with a surface of the substrate in the horizontal channel FET device region; forming a mask defining a first semiconductor structure mask portion above the vertical channel FET device region and a second semiconductor structure mask portion above the horizontal channel FET device region; and patterning the first layer structure and the second layer structure by simultaneously etching the first layer structure and the second layer structure while using the mask as an etch mask, thereby forming: a first semiconductor structure for a vertical channel FET device in the vertical channel FET device region, the first semiconductor structure comprising a lower layer portion, an intermediate layer portion and an upper layer portion, and a second semiconductor structure for a horizontal channel FET device in the horizontal channel FET device region.
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公开(公告)号：US10127961B2
公开(公告)日：2018-11-13
申请号：US15367293
申请日：2016-12-02
Applicant: IMEC VZW , Katholieke Universiteit Leuven, KU LEUVEN R&D
Inventor： Raf Appeltans , Praveen Raghavan
Abstract: Three transistor two junction magnetoresistive random-access memory (MRAM) bit cells provided. An example MRAM bit cell includes a first magnetic tunnel junction, MTJ, connected to a first bit line. The MRAM bit cell also includes a second MTJ connected to a second bit line. In addition, the MRAM bit cell includes a first transistor connected to the first MTJ and to a ground conductor. The MRAM bit cell further includes a second transistor connected to the second MTJ and to the ground conductor. Additionally, the MRAM bit cell includes a third transistor connected to the first transistor and to the second transistor.
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公开(公告)号：US20180248111A1
公开(公告)日：2018-08-30
申请号：US15904189
申请日：2018-02-23
Applicant: IMEC VZW , Katholieke Universiteit Leuven
Inventor： Praveen Raghavan , Davide Francesco Crotti , Raf Appeltans
Abstract: The disclosed technology generally relates to magnetoresistive devices, and more particularly to a magnetic tunnel junction (MTJ) device formed in an interconnection structure, and to a method of integrating the (MTJ) device in the interconnection structure. According to an aspect, a device includes a first interconnection level including a first dielectric layer and a first set of conductive paths arranged in the first dielectric layer, a second interconnection level arranged on the first connection level and including a second dielectric layer and a second set of conductive paths arranged in the second dielectric layer, and a third interconnection level arranged on the second interconnection level and including a third dielectric layer and a third set of conductive paths arranged in the third dielectric layer. The device additionally includes a magnetic tunnel junction (MTJ) device including a bottom layer, a top layer and an MTJ structure arranged between the bottom layer and the top layer, wherein the bottom layer is connected to a bottom layer contact portion of the first set of conductive paths and the top layer is connected to a top layer contact portion of the second or third set of conductive paths. The device further includes a multi-level via extending through the second dielectric layer and the third dielectric layer, between a first via contact portion of the first set of conductive paths and a second via contact portion of the third set of conductive paths, wherein a height of the MTJ device corresponds to, or is less than, a height of the multi-level via.
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公开(公告)号：US20170169873A1
公开(公告)日：2017-06-15
申请号：US15367293
申请日：2016-12-02
Applicant: IMEC VZW , Katholieke Universiteit Leuven, KU LEUVEN R&D
Inventor： Raf Appeltans , Praveen Raghavan
CPC classification number: G11C11/1675 , G11C11/1657 , G11C11/1659 , G11C11/1673
Abstract: Three transistor two junction magnetoresistive random-access memory (MRAM) bit cells are disclosed. An example MRAM bit cell includes a first magnetic tunnel junction, MTJ, connected to a first bit line. The MRAM bit cell also includes a second MTJ connected to a second bit line. In addition, the MRAM bit cell includes a first transistor connected to the first MTJ and to a ground conductor. The MRAM bit cell further includes a second transistor connected to the second MTJ and to the ground conductor. Additionally, the MRAM bit cell includes a third transistor connected to the first transistor and to the second transistor.
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