公开(公告)号：US11018235B2

公开(公告)日：2021-05-25

申请号：US15349904

申请日：2016-11-11

Applicant: IMEC VZW ,  Vrije Universiteit Brussel

Inventor： Trong Huynh Bao ,  Anabela Veloso ,  Julien Ryckaert

IPC: H01L29/423 ,  H01L23/528 ,  H01L29/06 ,  H01L29/786 ,  H01L27/11 ,  H01L29/775 ,  H01L29/66 ,  B82Y10/00 ,  H01L27/06 ,  H01L29/417

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to semiconductor devices having a stacked arrangement, and further relates to methods of fabricating such devices. In one aspect, a semiconductor device comprises a first memory device and a second memory device formed over a substrate and at least partly stacked in a vertical direction. Each of the first and second memory devices has a plurality of vertical transistors, wherein each vertical transistor has a vertical channel extending in the vertical direction.

公开(公告)号：US10957793B2

公开(公告)日：2021-03-23

申请号：US16128386

申请日：2018-09-11

Applicant: IMEC vzw

Inventor： Vasile Paraschiv ,  Guglielma Vecchio ,  Anabela Veloso

IPC: H01L29/78 ,  H01L21/311 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02

Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of forming a target layer surrounding a vertical nanostructure. In one aspect, a method includes providing a substrate having a substrate surface. The method additionally includes forming a vertical nanostructure extending outwardly from a substrate surface. The vertical nanostructure has a sidewall surface, where the sidewall surface has an upper portion and a lower portion. The method additionally includes forming a target layer at least along the sidewall surface of the vertical nanostructure and on the substrate surface. The method additionally includes forming a protection layer covering the target layer and removing an upper portion of the protection layer, thereby exposing the target layer along the upper portion of the sidewall surface of the vertical nanostructure. Thereafter, the exposed target layer is removed along the upper portion of the sidewall surface of the vertical nanostructure selective towards the protection layer. Thereafter, the remaining protection layer is removed.

公开(公告)号：US09633891B2

公开(公告)日：2017-04-25

申请号：US14924832

申请日：2015-10-28

Applicant: IMEC VZW

Inventor： Nadine Collaert ,  Geert Eneman ,  Naoto Horiguchi ,  Min-Soo Kim ,  Rita Rooyackers ,  Anabela Veloso ,  Liesbeth Witters

IPC: H01L21/762 ,  H01L21/32 ,  H01L21/3205 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/76224 ,  H01L21/32 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

公开(公告)号：US20160126131A1

公开(公告)日：2016-05-05

申请号：US14924832

申请日：2015-10-28

Applicant: IMEC VZW

Inventor： Nadine Collaert ,  Geert Eneman ,  Naoto Horiguchi ,  Min-Soo Kim ,  Rita Rooyackers ,  Anabela Veloso ,  Liesbeth Witters

IPC: H01L21/762 ,  H01L21/3205 ,  H01L29/06 ,  H01L21/32

CPC classification number: H01L21/76224 ,  H01L21/32 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

Abstract translation: 一个示例性方法包括在由相邻STI结构限定的沟槽中提供层堆叠，并使邻近层堆叠的STI结构凹陷，从而暴露层堆叠的上部，上部至少包括沟道部分。 该方法还包括在层堆叠的上部提供一个或多个保护层，然后进一步将STI结构选择性地凹入保护层和层堆叠，从而暴露层堆叠的中心部分。 并且该方法包括去除层堆叠的中心部分，导致层叠体的独立上部和下部在物理上彼此分离。

公开(公告)号：US20230142597A1

公开(公告)日：2023-05-11

申请号：US18048005

申请日：2022-10-19

Applicant: IMEC VZW

Inventor： Anabela Veloso ,  Eric Beyne ,  Anne Jourdain

IPC: H01L21/768 ,  H01L21/66 ,  H01L21/78

CPC classification number: H01L21/76877 ,  H01L21/78 ,  H01L21/76802 ,  H01L22/12

Abstract: A method of producing an IC chip is provided. In one aspect, deep trenches are formed in a semiconductor layer that forms the top layer of a device wafer, the trenches going through the complete thickness of the layer. The trenches are filled with a sacrificial material, that is etched back and covered with a capping layer, thereby forming sacrificial buried rails. After processing active devices on the front surface of the semiconductor layer, including connections to the sacrificial rails, the device wafer is bonded face down to a carrier wafer, and thinned from the back side, until the sacrificial rails are exposed. The sacrificial material and the capping layer are removed and replaced by a conductive material, thereby forming the actual buried power rails. A back side power delivery network supplies power through the buried rails to the active devices of the IC. Using a sacrificial material for the buried rails can enable a wider choice of materials for these buried rails.

公开(公告)号：US11217488B2

公开(公告)日：2022-01-04

申请号：US16835786

申请日：2020-03-31

Applicant: IMEC vzw

Inventor： Anabela Veloso ,  Trong Huynh Bao ,  Raf Appeltans

IPC: H01L21/8234 ,  H01L21/311

Abstract: The disclosed technology generally relates to semiconductor devices and methods of forming the same. In one aspect, a method of forming a semiconductor device having vertical channel field-effect transistor (FET) devices comprises forming on a substrate, a plurality of semiconductor structures protruding vertically from a lower source/drain semiconductor layer of the substrate. The semiconductor structures can be arranged in an array having a plurality of rows and columns. The method can include etching metal line trenches between at least a subset of the rows and forming metal lines in the metal line trenches to contact the lower source/drain layer. The method can also include forming gate structures at least partly enclosing semiconductor structure channel portions located above the lower source/drain layer and forming upper source/drain metal contacts on semiconductor structure upper source/drain portions located above the channel portions.

公开(公告)号：US20200312726A1

公开(公告)日：2020-10-01

申请号：US16836653

申请日：2020-03-31

Applicant: IMEC vzw

Inventor： Anabela Veloso ,  Trong Huynh Bao ,  Julien Ryckaert ,  Raf Appeltans

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method of fabricating a semiconductor device is disclosed. In one aspect, the method includes forming, in a vertical channel field-effect transistor (FET) device region, a vertical channel FET device including a first semiconductor structure including a lower source/drain portion, an upper source/drain portion, a first channel portion extending vertically and intermediate the source/drain portions and a gate structure extending along the channel portion and, in a horizontal channel FET device region, a horizontal channel FET device comprising a second semiconductor structure including a first source/drain portion, a second source/drain portion, a second channel portion extending horizontally and intermediate the source/drain portions, and a gate structure extending across the channel portion.

公开(公告)号：US20190097047A1

公开(公告)日：2019-03-28

申请号：US16128386

申请日：2018-09-11

Applicant: IMEC vzw

Inventor： Vasile Paraschiv ,  Guglielma Vecchio ,  Anabela Veloso

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02

Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of forming a target layer surrounding a vertical nanostructure. In one aspect, a method includes providing a substrate having a substrate surface. The method additionally includes forming a vertical nanostructure extending outwardly from a substrate surface. The vertical nanostructure has a sidewall surface, where the sidewall surface has an upper portion and a lower portion. The method additionally includes forming a target layer at least along the sidewall surface of the vertical nanostructure and on the substrate surface. The method additionally includes forming a protection layer covering the target layer and removing an upper portion of the protection layer, thereby exposing the target layer along the upper portion of the sidewall surface of the vertical nanostructure. Thereafter, the exposed target layer is removed along the upper portion of the sidewall surface of the vertical nanostructure selective towards the protection layer. Thereafter, the remaining protection layer is removed.

公开(公告)号：US11088263B2

公开(公告)日：2021-08-10

申请号：US16893233

申请日：2020-06-04

Applicant: IMEC vzw

Inventor： Anabela Veloso ,  Geert Eneman

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/417

Abstract: The disclosed technology relates generally to semiconductor processing and more particularly to a method of forming a vertical field-effect transistor device. According to an aspect, a method of forming a vertical field-effect transistor device comprises forming on a substrate a vertical semiconductor structure protruding above the substrate and comprising a lower source/drain portion, an upper source/drain portion and a channel portion arranged between the lower source/drain portion and the upper source/drain portion. The method additionally comprises forming on the channel portion an epitaxial semiconductor stressor layer enclosing the channel portion, wherein the stressor layer and the channel portion are lattice mismatched, forming an insulating layer and a sacrificial structure, wherein the sacrificial structure encloses the channel portion with the stressor layer formed thereon and wherein the insulating layer embeds the semiconductor structure and the sacrificial structure, forming in the insulating layer an opening exposing a surface portion of the sacrificial structure, and etching the sacrificial structure through the opening in the insulating layer, thereby forming a cavity exposing the stressor layer enclosing the channel portion. The method further comprises, subsequent to etching the sacrificial structure, etching the stressor layer in the cavity, and subsequent to etching the stressor layer, forming a gate stack in the cavity, wherein the gate stack encloses the channel portion of the vertical semiconductor structure.

公开(公告)号：US20200312725A1

公开(公告)日：2020-10-01

申请号：US16836478

申请日：2020-03-31

Applicant: IMEC vzw

Inventor： Anabela Veloso ,  Trong Huynh Bao ,  Julien Ryckaert ,  Raf Appeltans

IPC: H01L21/8234

Abstract: The disclosed technology relates to methods of fabricating field-effect transistors having channels extending in horizontal and vertical directions. According to an aspect, a method comprises: providing a semiconductor substrate comprising: in a vertical channel field-effect transistor (FET) device region, a first layer structure comprising a lower semiconductor layer, an intermediate semiconductor layer above the lower semiconductor layer and an upper semiconductor layer above the intermediate semiconductor layer, and, in a horizontal channel FET device region, a second layer structure comprising at least one semiconductor layer, wherein the first layer structure and the second layer structure have different compositions and wherein a surface of the substrate in the vertical channel FET device region is coplanar with a surface of the substrate in the horizontal channel FET device region; forming a mask defining a first semiconductor structure mask portion above the vertical channel FET device region and a second semiconductor structure mask portion above the horizontal channel FET device region; and patterning the first layer structure and the second layer structure by simultaneously etching the first layer structure and the second layer structure while using the mask as an etch mask, thereby forming: a first semiconductor structure for a vertical channel FET device in the vertical channel FET device region, the first semiconductor structure comprising a lower layer portion, an intermediate layer portion and an upper layer portion, and a second semiconductor structure for a horizontal channel FET device in the horizontal channel FET device region.