公开(公告)号：US20130075932A1

公开(公告)日：2013-03-28

申请号：US13623994

申请日：2012-09-21

Applicant: Infineon Technologies AG

Inventor： Ulrich Michael Georg Schwarzer ,  Daniel Bolowski

IPC: H01L23/522

CPC classification number: H01L23/5226 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49844 ,  H01L25/072 ,  H01L2224/24 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A power semiconductor module includes a first printed circuit board having a first insulation carrier, and a first upper metallization and a first lower metallization applied to the first insulation carrier on mutually opposite sides, and a second printed circuit board having a second insulation carrier and a second upper metallization applied to the second insulation carrier. The second printed circuit board is spaced apart from the first printed circuit board in a vertical direction oriented perpendicular to the opposite sides of the first insulation carrier. A semiconductor chip is disposed between the printed circuit boards and electrically conductively connected at least to the second upper metallization. The first lower metallization and the second upper metallization face one another. The first printed circuit board has a first thick conductor layer at least partly embedded in the first insulation carrier and which has a thickness of at least 100 μm.

Abstract translation: 功率半导体模块包括第一印刷电路板，第一印刷电路板具有第一绝缘载体，第一上部金属化和第一下部金属化，其在彼此相对的两侧施加到第一绝缘载体，第二印刷电路板具有第二绝缘载体和 施加到第二绝缘载体的第二上金属化。 第二印刷电路板在垂直于第一绝缘载体的相对侧定向的垂直方向上与第一印刷电路板间隔开。 半导体芯片设置在印刷电路板之间并且至少电连接到第二上金属化层。 第一下部金属化和第二上部金属化面向彼此。 第一印刷电路板具有至少部分地嵌入第一绝缘载体中并具有至少100μm的厚度的第一厚导体层。

公开(公告)号：US20130285712A1

公开(公告)日：2013-10-31

申请号：US13871288

申请日：2013-04-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Peter Kanschat ,  Andre Arens ,  Hartmut Jasberg ,  Ulrich Michael Georg Schwarzer

IPC: H03K17/00

CPC classification number: H03K17/00 ,  H03K17/163 ,  H03K17/168

Abstract: A method for driving a controllable power semiconductor switch, having a first input terminal and first and second output terminals coupled to a voltage supply and a load, the first and second output terminals providing an output of the power semiconductor switch, includes adjusting a gradient of switch-off edges of an output current and an output voltage of the power semiconductor switch by a voltage source arrangement coupled to the input terminal. A gradient of switch-on edges of an output current and an output voltage is adjusted by a controllable current source arrangement that is coupled to the input terminal and generates a gate drive current. The profile of the gate drive current from one switching operation to a subsequent switching operation, beginning at a rise in the output current and ending at a decrease in the output voltage, is varied at most within a predefined tolerance band.

Abstract translation: 一种用于驱动可控功率半导体开关的方法，具有第一输入端和耦合到电压源和负载的第一和第二输出端，提供功率半导体开关的输出的第一和第二输出端包括： 通过耦合到输入端的电压源装置，输出电流的关断边缘和功率半导体开关的输出电压。 输出电流和输出电压的接通边沿的梯度由耦合到输入端子的可控电流源装置调节并产生栅极驱动电流。 从输出电流的上升开始并以输出电压的降低结束的栅极驱动电流从一个开关操作到随后的开关操作的曲线最多在预定义的公差带内变化。

公开(公告)号：US12041755B2

公开(公告)日：2024-07-16

申请号：US18082795

申请日：2022-12-16

Applicant: Infineon Technologies AG

Inventor： Regina Nottelmann ,  Andre Arens ,  Michael Ebli ,  Alexander Herbrandt ,  Ulrich Michael Georg Schwarzer ,  Alparslan Takkac

IPC: H05K7/20 ,  H05K1/18 ,  H05K3/30

CPC classification number: H05K7/2039 ,  H05K1/181 ,  H05K3/303

Abstract: A method for producing a power semiconductor module arrangement includes: arranging at least one semiconductor substrate in a housing, each semiconductor substrate including a first metallization layer attached to a dielectric insulation layer, the housing including a through hole extending through a component of the housing; inserting a fastener into the through hole such that an upper portion of the fastener is not inserted into the through hole; arranging a printed circuit board on the housing; arranging the housing on a mounting surface, the mounting surface comprising a hole, wherein the housing is arranged on the mounting surface such that the through hole is aligned with the hole in the mounting surface; and exerting a force on the printed circuit board such that the force causes the fastener to be pressed into the hole in the mounting surface so as to secure the housing to the mounting surface.

公开(公告)号：US20230124688A1

公开(公告)日：2023-04-20

申请号：US18082795

申请日：2022-12-16

Applicant: Infineon Technologies AG

Inventor： Regina Nottelmann ,  Andre Arens ,  Michael Ebli ,  Alexander Herbrandt ,  Ulrich Michael Georg Schwarzer ,  Alparslan Takkac

IPC: H05K7/20 ,  H05K1/18 ,  H05K3/30

Abstract: A method for producing a power semiconductor module arrangement includes: arranging at least one semiconductor substrate in a housing, each semiconductor substrate including a first metallization layer attached to a dielectric insulation layer, the housing including a through hole extending through a component of the housing; inserting a fastener into the through hole such that an upper portion of the fastener is not inserted into the through hole; arranging a printed circuit board on the housing; arranging the housing on a mounting surface, the mounting surface comprising a hole, wherein the housing is arranged on the mounting surface such that the through hole is aligned with the hole in the mounting surface; and exerting a force on the printed circuit board such that the force causes the fastener to be pressed into the hole in the mounting surface so as to secure the housing to the mounting surface.

公开(公告)号：US20210400838A1

公开(公告)日：2021-12-23

申请号：US17346841

申请日：2021-06-14

Applicant: Infineon Technologies AG

Inventor： Regina Nottelmann ,  Andre Arens ,  Michael Ebli ,  Alexander Herbrandt ,  Ulrich Michael Georg Schwarzer ,  Alparslan Takkac

IPC: H05K7/20 ,  H05K3/30 ,  H05K1/18

Abstract: A method for producing a power semiconductor module arrangement includes: arranging a semiconductor substrate in a housing, the housing including a through hole extending through a component of the housing; inserting a pin or bolt into the through hole such that an upper end of the pin/bolt is not inserted into the through hole; arranging a printed circuit board on the housing; arranging the housing on a heat sink having a hole, the housing being arranged on the heat sink such that the through hole is aligned with the hole in the heat sink; and by way of a first pressing tool, exerting a force on a defined contact area of the printed circuit board and pressing the pin/bolt into the hole in the heat sink, wherein the defined contact area is arranged directly above the pin/bolt.

公开(公告)号：US08981553B2

公开(公告)日：2015-03-17

申请号：US13623994

申请日：2012-09-21

Applicant: Infineon Technologies AG

Inventor： Ulrich Michael Georg Schwarzer ,  Daniel Bolowski

IPC: H01L23/053 ,  H01L23/48 ,  H01L23/522 ,  H01L23/36 ,  H01L23/373 ,  H01L23/498 ,  H01L25/07

CPC classification number: H01L23/5226 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49844 ,  H01L25/072 ,  H01L2224/24 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A power semiconductor module includes a first printed circuit board having a first insulation carrier, and a first upper metallization and a first lower metallization applied to the first insulation carrier on mutually opposite sides, and a second printed circuit board having a second insulation carrier and a second upper metallization applied to the second insulation carrier. The second printed circuit board is spaced apart from the first printed circuit board in a vertical direction oriented perpendicular to the opposite sides of the first insulation carrier. A semiconductor chip is disposed between the printed circuit boards and electrically conductively connected at least to the second upper metallization. The first lower metallization and the second upper metallization face one another. The first printed circuit board has a first thick conductor layer at least partly embedded in the first insulation carrier and which has a thickness of at least 100 μm.

Abstract translation: 功率半导体模块包括第一印刷电路板，第一印刷电路板具有第一绝缘载体，第一上部金属化和第一下部金属化，其在彼此相对的两侧施加到第一绝缘载体，第二印刷电路板具有第二绝缘载体和 施加到第二绝缘载体的第二上金属化。 第二印刷电路板在垂直于第一绝缘载体的相对侧定向的垂直方向上与第一印刷电路板间隔开。 半导体芯片设置在印刷电路板之间并且至少电连接到第二上金属化层。 第一下部金属化和第二上部金属化面向彼此。 第一印刷电路板具有至少部分地嵌入第一绝缘载体中并具有至少100μm的厚度的第一厚导体层。

公开(公告)号：US11533824B2

公开(公告)日：2022-12-20

申请号：US17346841

申请日：2021-06-14

Applicant: Infineon Technologies AG

Inventor： Regina Nottelmann ,  Andre Arens ,  Michael Ebli ,  Alexander Herbrandt ,  Ulrich Michael Georg Schwarzer ,  Alparslan Takkac

IPC: H05K7/20 ,  H05K1/18 ,  H05K3/30

Abstract: A method for producing a power semiconductor module arrangement includes: arranging a semiconductor substrate in a housing, the housing including a through hole extending through a component of the housing; inserting a pin or bolt into the through hole such that an upper end of the pin/bolt is not inserted into the through hole; arranging a printed circuit board on the housing; arranging the housing on a heat sink having a hole, the housing being arranged on the heat sink such that the through hole is aligned with the hole in the heat sink; and by way of a first pressing tool, exerting a force on a defined contact area of the printed circuit board and pressing the pin/bolt into the hole in the heat sink, wherein the defined contact area is arranged directly above the pin/bolt.