公开(公告)号：US11978700B2

公开(公告)日：2024-05-07

申请号：US17872255

申请日：2022-07-25

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/24 ,  H01L23/31 ,  H01L23/367 ,  H01L23/40 ,  H01L23/498 ,  H01L25/07 ,  H01L23/00

CPC classification number: H01L23/49861 ,  H01L21/568 ,  H01L23/24 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/3672 ,  H01L23/4006 ,  H01L23/49844 ,  H01L25/072 ,  H01L23/564 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091

Abstract: A power semiconductor module arrangement includes two or more individual semiconductor devices arranged on a base layer. Each semiconductor device includes a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame. A frame is arranged on the base layer such that the frame surrounds the two or more individual semiconductor devices. A casting compound at least partly fills a capacity formed by the base layer and the frame, such that the casting compound at least partly encloses the two or more individual semiconductor devices.

公开(公告)号：US20190189553A1

公开(公告)日：2019-06-20

申请号：US16220956

申请日：2018-12-14

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/40 ,  H01L23/31 ,  H01L23/24

CPC classification number: H01L23/49861 ,  H01L21/568 ,  H01L23/24 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/3672 ,  H01L23/4006 ,  H01L23/49844 ,  H01L23/564 ,  H01L25/072 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091

Abstract: A power semiconductor module arrangement including two or more individual semiconductor devices each semiconductor device having a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame. The power semiconductor module arrangement further includes a frame surrounding the two or more individual semiconductor devices, and a casting compound at least partly filling a capacity within the frame, thereby at least partly enclosing the two or more individual semiconductor devices.

公开(公告)号：US09891247B2

公开(公告)日：2018-02-13

申请号：US14497437

申请日：2014-09-26

Applicant: Infineon Technologies AG

Inventor： Peter Kanschat ,  Thilo Stolze

IPC: G01R1/20 ,  G01R19/00 ,  H01C17/00 ,  H01C1/144

CPC classification number: G01R1/203 ,  G01R19/0092 ,  H01C1/144 ,  H01C17/00 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/49107 ,  H01L2924/13055 ,  Y10T29/49082 ,  H01L2924/00

Abstract: A measurement resistor for current measurement is described. According to one exemplary embodiment, the measurement resistor includes a first and a second metal layer, an electrically insulating interlayer and a resistive layer. The first metal layer is arranged in a first plane. The second metal layer is arranged in a second plane that is essentially parallel to the first plane and separated from the first plane. The electrically insulating interlayer is arranged between the first and second metal layers and mechanically connects the first and second metal layers to one another. The resistive layer electrically connects the first and second metal layers to one another.

公开(公告)号：US20130285712A1

公开(公告)日：2013-10-31

申请号：US13871288

申请日：2013-04-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Peter Kanschat ,  Andre Arens ,  Hartmut Jasberg ,  Ulrich Michael Georg Schwarzer

IPC: H03K17/00

CPC classification number: H03K17/00 ,  H03K17/163 ,  H03K17/168

Abstract: A method for driving a controllable power semiconductor switch, having a first input terminal and first and second output terminals coupled to a voltage supply and a load, the first and second output terminals providing an output of the power semiconductor switch, includes adjusting a gradient of switch-off edges of an output current and an output voltage of the power semiconductor switch by a voltage source arrangement coupled to the input terminal. A gradient of switch-on edges of an output current and an output voltage is adjusted by a controllable current source arrangement that is coupled to the input terminal and generates a gate drive current. The profile of the gate drive current from one switching operation to a subsequent switching operation, beginning at a rise in the output current and ending at a decrease in the output voltage, is varied at most within a predefined tolerance band.

Abstract translation: 一种用于驱动可控功率半导体开关的方法，具有第一输入端和耦合到电压源和负载的第一和第二输出端，提供功率半导体开关的输出的第一和第二输出端包括： 通过耦合到输入端的电压源装置，输出电流的关断边缘和功率半导体开关的输出电压。 输出电流和输出电压的接通边沿的梯度由耦合到输入端子的可控电流源装置调节并产生栅极驱动电流。 从输出电流的上升开始并以输出电压的降低结束的栅极驱动电流从一个开关操作到随后的开关操作的曲线最多在预定义的公差带内变化。

公开(公告)号：US20220359365A1

公开(公告)日：2022-11-10

申请号：US17872255

申请日：2022-07-25

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/40 ,  H01L23/31 ,  H01L23/24 ,  H01L21/56 ,  H01L25/07

Abstract: A power semiconductor module arrangement includes two or more individual semiconductor devices arranged on a base layer. Each semiconductor device includes a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame. A frame is arranged on the base layer such that the frame surrounds the two or more individual semiconductor devices. A casting compound at least partly fills a capacity formed by the base layer and the frame, such that the casting compound at least partly encloses the two or more individual semiconductor devices.

公开(公告)号：US20210074624A1

公开(公告)日：2021-03-11

申请号：US16951556

申请日：2020-11-18

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/40 ,  H01L23/31 ,  H01L23/24 ,  H01L21/56 ,  H01L25/07

Abstract: A method for producing a power semiconductor module arrangement includes arranging two or more individual semiconductor devices on a base layer, each semiconductor device including a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame, arranging a frame on the base layer such that the frame surrounds the two or more individual semiconductor devices, and filling a first material into a capacity formed by the base layer and the frame, and hardening the first material to form a casting compound that at least partly fills the capacity, thereby at least partly encloses the two or more individual semiconductor devices.

公开(公告)号：US09559065B2

公开(公告)日：2017-01-31

申请号：US14476241

申请日：2014-09-03

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/07 ,  H01L25/00 ,  H01L23/051 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly.

公开(公告)号：US20150061100A1

公开(公告)日：2015-03-05

申请号：US14477386

申请日：2014-09-04

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L25/07 ,  H01L23/495 ,  H01L23/492 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/072 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/48 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/562 ,  H01L24/24 ,  H01L24/33 ,  H01L24/72 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/29011 ,  H01L2224/32245 ,  H01L2224/82039 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00

Abstract: A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assembly has a semiconductor chip having a semiconductor body. The semiconductor body has a top side and an opposing underside. The top side is spaced apart from the underside in a vertical direction. Each semiconductor chip has a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, a control electrode arranged at the top side, and an electrically conductive top compensation die, arranged on the side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer. An electric current between the top main electrode and the bottom main electrode can be controlled by means of the control electrode.

Abstract translation: 半导体装置包括顶部和底部接触板，多个芯片组件，电介质嵌入化合物和控制电极互连结构。 每个芯片组件具有半导体芯片，该半导体芯片具有半导体本体。 半导体本体具有顶侧和相对的下侧。 顶侧在垂直方向上与下侧隔开。 每个半导体芯片具有布置在顶侧的顶部主电极，设置在下侧的底部主电极，布置在顶侧的控制电极和布置在顶部主电极对面侧的导电顶部补偿裸片 远离半导体本体并且通过顶部连接层内导电地连接到顶部主电极。 可以通过控制电极来控制顶部主电极和底部主电极之间的电流。

公开(公告)号：US20150162407A1

公开(公告)日：2015-06-11

申请号：US14102955

申请日：2013-12-11

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Roman Baburske ,  Peter Kanschat

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/861 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/1095 ,  H01L29/04 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/423 ,  H01L29/42368 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/8613

Abstract: A semiconductor device includes a drift zone in a semiconductor body. A charge-carrier transfer region forms a pn junction with the drift zone in the semiconductor body. A control structure electrically connects a recombination region to the drift zone during a desaturation cycle and disconnects the recombination region from the drift zone outside the desaturation cycle. During the desaturation cycle the recombination region reduces a charge carrier plasma in the drift zone and reduces reverse recovery losses without adversely affecting blocking characteristics.

Abstract translation: 半导体器件包括半导体本体中的漂移区。 电荷载流子传输区域与半导体本体中的漂移区形成pn结。 控制结构在去饱和循环期间将复合区域电连接到漂移区，并且将去除饱和循环以外的漂移区域的重组区域断开。 在去饱和循环期间，重组区域减少漂移区中的载流子等离子体并且减少反向回复损耗而不会不利地影响阻塞特性。

公开(公告)号：US20150091551A1

公开(公告)日：2015-04-02

申请号：US14497437

申请日：2014-09-26

Applicant: Infineon Technologies AG

Inventor： Peter Kanschat ,  Thilo Stolze

IPC: G01R1/20 ,  H01C17/00 ,  G01R19/00

CPC classification number: G01R1/203 ,  G01R19/0092 ,  H01C1/144 ,  H01C17/00 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/49107 ,  H01L2924/13055 ,  Y10T29/49082 ,  H01L2924/00

Abstract: A measurement resistor for current measurement is described. According to one exemplary embodiment, the measurement resistor includes a first and a second metal layer, an electrically insulating interlayer and a resistive layer. The first metal layer is arranged in a first plane. The second metal layer is arranged in a second plane that is essentially parallel to the first plane and separated from the first plane. The electrically insulating interlayer is arranged between the first and second metal layers and mechanically connects the first and second metal layers to one another. The resistive layer electrically connects the first and second metal layers to one another.

Abstract translation: 描述用于电流测量的测量电阻器。 根据一个示例性实施例，测量电阻器包括第一和第二金属层，电绝缘中间层和电阻层。 第一金属层布置在第一平面中。 第二金属层布置在基本上平行于第一平面并与第一平面分离的第二平面中。 电绝缘中间层布置在第一和第二金属层之间并将第一和第二金属层彼此机械连接。 电阻层将第一和第二金属层彼此电连接。