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公开(公告)号：US12041755B2
公开(公告)日：2024-07-16
申请号：US18082795
申请日：2022-12-16
Applicant: Infineon Technologies AG
Inventor： Regina Nottelmann , Andre Arens , Michael Ebli , Alexander Herbrandt , Ulrich Michael Georg Schwarzer , Alparslan Takkac
CPC classification number: H05K7/2039 , H05K1/181 , H05K3/303
Abstract: A method for producing a power semiconductor module arrangement includes: arranging at least one semiconductor substrate in a housing, each semiconductor substrate including a first metallization layer attached to a dielectric insulation layer, the housing including a through hole extending through a component of the housing; inserting a fastener into the through hole such that an upper portion of the fastener is not inserted into the through hole; arranging a printed circuit board on the housing; arranging the housing on a mounting surface, the mounting surface comprising a hole, wherein the housing is arranged on the mounting surface such that the through hole is aligned with the hole in the mounting surface; and exerting a force on the printed circuit board such that the force causes the fastener to be pressed into the hole in the mounting surface so as to secure the housing to the mounting surface.
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公开(公告)号：US20230124688A1
公开(公告)日：2023-04-20
申请号：US18082795
申请日：2022-12-16
Applicant: Infineon Technologies AG
Inventor： Regina Nottelmann , Andre Arens , Michael Ebli , Alexander Herbrandt , Ulrich Michael Georg Schwarzer , Alparslan Takkac
Abstract: A method for producing a power semiconductor module arrangement includes: arranging at least one semiconductor substrate in a housing, each semiconductor substrate including a first metallization layer attached to a dielectric insulation layer, the housing including a through hole extending through a component of the housing; inserting a fastener into the through hole such that an upper portion of the fastener is not inserted into the through hole; arranging a printed circuit board on the housing; arranging the housing on a mounting surface, the mounting surface comprising a hole, wherein the housing is arranged on the mounting surface such that the through hole is aligned with the hole in the mounting surface; and exerting a force on the printed circuit board such that the force causes the fastener to be pressed into the hole in the mounting surface so as to secure the housing to the mounting surface.
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3.发明授权公开(公告)号：US10972088B1
公开(公告)日：2021-04-06
申请号：US17009685
申请日：2020-09-01
Applicant: Infineon Technologies AG
Inventor： Jens Barrenscheen , Andre Arens
IPC: G01K7/16 , H03K17/082 , G01R27/16 , H03K17/08
Abstract: This disclosure is directed to circuits and techniques for detecting or responding to temperature of a power switch based on paired measurements of current and voltage. A driver circuit for a power switch may be configured to perform a current measurement and a voltage measurement associated with a temperature-dependent circuit element and control the power switch based at least in part on the current measurement and the voltage measurement. In some examples, the current and voltage measurements may be used to determine the temperature of the power switch.
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公开(公告)号：US10964642B2
公开(公告)日：2021-03-30
申请号：US15877749
申请日：2018-01-23
Applicant: Infineon Technologies AG
Inventor： Juergen Hoegerl , Andre Arens , Holger Torwesten
IPC: H01L23/29 , H01L23/34 , H01L23/498 , H01L23/373 , H01L25/16 , H01L23/48 , H01L23/31 , H01L23/538 , H01L23/00 , H01L21/48 , H01L21/56 , H01L23/433 , H01L23/495 , H01L23/50
Abstract: A semiconductor module is disclosed. In one example, the module includes a carrier, at least one semiconductor transistor disposed on the carrier, at least one semiconductor diode disposed on the carrier, at least one semiconductor driver chip disposed on the carrier, a plurality of external connectors, and an encapsulation layer covering the carrier, the semiconductor transistor, the semiconductor diode, and the semiconductor driver chip. The semiconductor transistor, the semiconductor diode, and the semiconductor driver chip are arranged laterally side by side on the carrier.
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5.发明公开公开(公告)号：US20230343681A1
公开(公告)日：2023-10-26
申请号：US18138245
申请日：2023-04-24
Applicant: Infineon Technologies AG
Inventor： Andre Arens , Martin Goldammer
CPC classification number: H01L23/49 , H01L25/072 , H01L24/32 , H01L24/48 , H01L24/73 , H01L21/565 , H01L2224/32225 , H01L2224/48155 , H01L2224/73265 , H01L2924/182
Abstract: A power semiconductor module arrangement includes a housing that includes sidewalls, a lid, protrusions, a substrate, a plurality of components arranged on the substrate, and an encapsulant partly filling the interior of the housing, thereby covering the substrate, wherein each of the protrusions extends from the lid of the housing, a lower end of the protrusions is arranged directly on one of the components, or within a defined radius around one of the components, and wherein the lower end of a protrusion is the end facing away from the lid and towards the substrate, and the encapsulant has a generally flat surface and forms one or more elevations, wherein each of the elevations encloses an upper end of a different one of the components, and encloses the lower end of a respective one of the protrusions.
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Patent Agency Ranking
公开(公告)号：US20210400838A1
公开(公告)日：2021-12-23
申请号：US17346841
申请日：2021-06-14
Applicant: Infineon Technologies AG
Inventor： Regina Nottelmann , Andre Arens , Michael Ebli , Alexander Herbrandt , Ulrich Michael Georg Schwarzer , Alparslan Takkac
Abstract: A method for producing a power semiconductor module arrangement includes: arranging a semiconductor substrate in a housing, the housing including a through hole extending through a component of the housing; inserting a pin or bolt into the through hole such that an upper end of the pin/bolt is not inserted into the through hole; arranging a printed circuit board on the housing; arranging the housing on a heat sink having a hole, the housing being arranged on the heat sink such that the through hole is aligned with the hole in the heat sink; and by way of a first pressing tool, exerting a force on a defined contact area of the printed circuit board and pressing the pin/bolt into the hole in the heat sink, wherein the defined contact area is arranged directly above the pin/bolt.
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7.发明申请公开(公告)号：US20200049569A1
公开(公告)日：2020-02-13
申请号：US16535381
申请日：2019-08-08
Applicant: Infineon Technologies AG
Inventor： Andre Arens , Waldemar Jakobi
IPC: G01K7/01 , H01L29/739 , H01L23/34 , H01L29/66 , H01L25/18 , H01L23/00 , H01L29/417 , H03K17/0812 , G01R19/14
Abstract: A power semiconductor circuit includes: a power semiconductor element having a gate electrode configured to actuate the power semiconductor element, a collector electrode, and an emitter electrode electrically connected to a first emitter terminal; and a temperature sensor having a first measurement point with a measurement terminal and a second measurement point electrically connected to the emitter electrode, so that a voltage which drops over the temperature sensor is measurable between the measurement terminal and the first emitter terminal for the temperature measurement. Corresponding methods for determining a temperature of a power semiconductor element and for determining a sign of a load current in a bridge circuit are also described.
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公开(公告)号：US20150342055A1
公开(公告)日：2015-11-26
申请号：US14709605
申请日：2015-05-12
Applicant: Infineon Technologies AG
Inventor： Andre Arens
IPC: H05K1/18 , H01L23/495
CPC classification number: H05K1/185 , H01L23/4952 , H01L23/49541 , H01L23/49575 , H01L23/49844 , H01L23/5386 , H01L23/5389 , H01L25/072 , H01L2924/0002 , H05K2201/10507 , H01L2924/00
Abstract: A semiconductor module includes a printed circuit board, and first and second embedded semiconductor chips. The first and second semiconductor chips each have a first load connection and a second load connection. The printed circuit board further includes a structured first metalization layer, which has a first section and a second section, and a structured second metalization layer, which has a first section, a second section and a third section. The first section of the second metalization layer and the second section of the first metalization layer have comb shaped structures having first and second protrusions. These first and second sections are electrically conductively connected to one another by a number of first plated-through holes each of which is permanently electrically conductively connected both at first protrusions to the first section of the second metalization layer and at second protrusions to the second section of the first metalization layer.
Abstract translation: 半导体模块包括印刷电路板，以及第一和第二嵌入式半导体芯片。 第一和第二半导体芯片各自具有第一负载连接和第二负载连接。 印刷电路板还包括具有第一部分和第二部分的结构化的第一金属化层和具有第一部分，第二部分和第三部分的结构化的第二金属化层。 第二金属化层的第一部分和第一金属化层的第二部分具有具有第一和第二突起的梳状结构。 这些第一和第二部分通过多个第一电镀通孔彼此导电连接，每个第一电镀通孔在第一突起处与第二金属化层的第一部分永久地导电连接，并且在第二突起处连接到第二部分 的第一金属化层。
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公开(公告)号：US12256514B2
公开(公告)日：2025-03-18
申请号：US17537959
申请日：2021-11-30
Applicant: Infineon Technologies AG
Inventor： Andre Arens
Abstract: An apparatus comprises a power module housing. The power module housing includes a conductive substrate and a circuit board positioned overlying the conductive substrate. A gate driver is mounted to the circuit board. A power device is mounted to the conductive substrate and is controlled by the gate driver. The power module housing includes an insulation material electrically insulating the conductive substrate from the circuit board. A monitoring component is mounted to at least the conductive substrate and is operatively coupled to the gate driver and the power device.
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公开(公告)号：US11856718B2
公开(公告)日：2023-12-26
申请号：US18070849
申请日：2022-11-29
Applicant: Infineon Technologies AG
Inventor： Alexander Herbrandt , Philipp Bräutigam , Andre Arens , Marco Ludwig
CPC classification number: H05K5/0026 , H01L23/4006 , H05K5/0247 , H05K7/209 , H01L23/49811 , H01L24/48 , H01L25/072 , H01L2224/48225
Abstract: An arrangement includes a housing and a printed circuit board (PCB) arranged vertically above the housing. The housing includes: at least one protrusion attached to sidewalls and arranged on an outside of the housing at a lower end with at least one first through hole provided in the protrusion; holding devices each arranged inside a first through hole and/or between the PCB and the first through hole; and fastening elements configured to attach the housing to a heat sink or base plate. Each holding device is configured to clamp a corresponding fastening element such that the fastening elements are secured in defined positions, and to align each fastening element with a different first through hole. The PCB includes second through holes each arranged vertically above and aligned with a different fastening element. A diameter of each second through hole is less than the largest diameter of the respective fastening element.
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