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1.发明申请公开(公告)号：US20130075932A1
公开(公告)日：2013-03-28
申请号：US13623994
申请日：2012-09-21
Applicant: Infineon Technologies AG
Inventor： Ulrich Michael Georg Schwarzer , Daniel Bolowski
IPC: H01L23/522
CPC classification number: H01L23/5226 , H01L23/36 , H01L23/3735 , H01L23/49811 , H01L23/49827 , H01L23/49833 , H01L23/49844 , H01L25/072 , H01L2224/24 , H01L2924/1301 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/00
Abstract: A power semiconductor module includes a first printed circuit board having a first insulation carrier, and a first upper metallization and a first lower metallization applied to the first insulation carrier on mutually opposite sides, and a second printed circuit board having a second insulation carrier and a second upper metallization applied to the second insulation carrier. The second printed circuit board is spaced apart from the first printed circuit board in a vertical direction oriented perpendicular to the opposite sides of the first insulation carrier. A semiconductor chip is disposed between the printed circuit boards and electrically conductively connected at least to the second upper metallization. The first lower metallization and the second upper metallization face one another. The first printed circuit board has a first thick conductor layer at least partly embedded in the first insulation carrier and which has a thickness of at least 100 μm.
Abstract translation: 功率半导体模块包括第一印刷电路板，第一印刷电路板具有第一绝缘载体，第一上部金属化和第一下部金属化，其在彼此相对的两侧施加到第一绝缘载体，第二印刷电路板具有第二绝缘载体和 施加到第二绝缘载体的第二上金属化。 第二印刷电路板在垂直于第一绝缘载体的相对侧定向的垂直方向上与第一印刷电路板间隔开。 半导体芯片设置在印刷电路板之间并且至少电连接到第二上金属化层。 第一下部金属化和第二上部金属化面向彼此。 第一印刷电路板具有至少部分地嵌入第一绝缘载体中并具有至少100μm的厚度的第一厚导体层。
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Patent Agency Ranking
公开(公告)号：US20150333034A1
公开(公告)日：2015-11-19
申请号：US14708964
申请日：2015-05-11
Applicant: Infineon Technologies AG
Inventor： Daniel Bolowski , Achim Froemelt , Christian Kersting , Christian Stahlhut
CPC classification number: B22F1/0074 , B23K1/0016 , B23K1/203 , H01L21/00 , H01L24/29 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/83 , H01L24/85 , H01L2224/29026 , H01L2224/32225 , H01L2224/37124 , H01L2224/37147 , H01L2224/40095 , H01L2224/40225 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L2224/83065 , H01L2224/83359 , H01L2224/8384 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2224/92246 , H01L2224/92247 , H01L2924/00014 , H01L2924/01029 , H01L2924/13055 , H01L2924/13091 , H01L2924/19107 , H01L2924/00 , H01L2224/45015 , H01L2924/207
Abstract: A method includes providing a subassembly having a circuit carrier with a first metallic surface portion, a first joining partner, which is integrally connected to the first metallic surface portion by means of a first connecting layer, and a second metallic surface portion. In a heat treatment, the second metallic surface portion is held uninterruptedly at temperatures which are higher than a minimum heat-treatment temperature of at least 300° C. Moreover, a second joining partner is provided. A fixed connection is produced between the second joining partner and the subassembly in that the second joining partner is integrally connected to the subassembly following completion of the heat treatment on the second surface portion.
Abstract translation: 一种方法包括提供具有第一金属表面部分的电路载体的子组件，通过第一连接层与第一金属表面部分一体地连接的第一接合配合体和第二金属表面部分。 在热处理中，第二金属表面部分在高于至少300℃的最小热处理温度的温度下不间断地保持。此外，提供第二接合对象。 在第二接合伙伴和子组件之间产生固定连接，因为在第二表面部分上的热处理完成之后，第二接合伙伴一体地连接到子组件。
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3.发明授权公开(公告)号：US08981553B2
公开(公告)日：2015-03-17
申请号：US13623994
申请日：2012-09-21
Applicant: Infineon Technologies AG
Inventor： Ulrich Michael Georg Schwarzer , Daniel Bolowski
IPC: H01L23/053 , H01L23/48 , H01L23/522 , H01L23/36 , H01L23/373 , H01L23/498 , H01L25/07
CPC classification number: H01L23/5226 , H01L23/36 , H01L23/3735 , H01L23/49811 , H01L23/49827 , H01L23/49833 , H01L23/49844 , H01L25/072 , H01L2224/24 , H01L2924/1301 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/00
Abstract: A power semiconductor module includes a first printed circuit board having a first insulation carrier, and a first upper metallization and a first lower metallization applied to the first insulation carrier on mutually opposite sides, and a second printed circuit board having a second insulation carrier and a second upper metallization applied to the second insulation carrier. The second printed circuit board is spaced apart from the first printed circuit board in a vertical direction oriented perpendicular to the opposite sides of the first insulation carrier. A semiconductor chip is disposed between the printed circuit boards and electrically conductively connected at least to the second upper metallization. The first lower metallization and the second upper metallization face one another. The first printed circuit board has a first thick conductor layer at least partly embedded in the first insulation carrier and which has a thickness of at least 100 μm.
Abstract translation: 功率半导体模块包括第一印刷电路板，第一印刷电路板具有第一绝缘载体，第一上部金属化和第一下部金属化，其在彼此相对的两侧施加到第一绝缘载体，第二印刷电路板具有第二绝缘载体和 施加到第二绝缘载体的第二上金属化。 第二印刷电路板在垂直于第一绝缘载体的相对侧定向的垂直方向上与第一印刷电路板间隔开。 半导体芯片设置在印刷电路板之间并且至少电连接到第二上金属化层。 第一下部金属化和第二上部金属化面向彼此。 第一印刷电路板具有至少部分地嵌入第一绝缘载体中并具有至少100μm的厚度的第一厚导体层。
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公开(公告)号：US11410950B2
公开(公告)日：2022-08-09
申请号：US17023538
申请日：2020-09-17
Applicant: Infineon Technologies AG
Inventor： Gert Pfahl , Daniel Bolowski , Marian Sebastian Broll , Michael Kreuz , Evelyn Napetschnig , Holger Schulze , Stefan Woehlert
Abstract: A semiconductor substrate has a bond pad. The bond pad includes a layer of an aluminum alloy having a chemical composition including at least 0.3% by weight of at least one of Zn, Mg, Sc, Zr, Ti, Ag and/or Mn, with the balance being at least Al and incidental impurities.
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公开(公告)号：US20210091025A1
公开(公告)日：2021-03-25
申请号：US17023538
申请日：2020-09-17
Applicant: Infineon Technologies AG
Inventor： Gert Pfahl , Daniel Bolowski , Marian Sebastian Broll , Michael Kreuz , Evelyn Napetschnig , Holger Schulze , Stefan Woehlert
Abstract: A semiconductor substrate has a bond pad. The bond pad includes a layer of an aluminum alloy having a chemical composition including at least 0.3% by weight of at least one of Zn, Mg, Sc, Zr, Ti, Ag and/or Mn, with the balance being at least Al and incidental impurities.
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公开(公告)号：US09925588B2
公开(公告)日：2018-03-27
申请号：US14708964
申请日：2015-05-11
Applicant: Infineon Technologies AG
Inventor： Daniel Bolowski , Achim Froemelt , Christian Kersting , Christian Stahlhut
CPC classification number: B22F1/0074 , B23K1/0016 , B23K1/203 , H01L21/00 , H01L24/29 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/83 , H01L24/85 , H01L2224/29026 , H01L2224/32225 , H01L2224/37124 , H01L2224/37147 , H01L2224/40095 , H01L2224/40225 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L2224/83065 , H01L2224/83359 , H01L2224/8384 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2224/92246 , H01L2224/92247 , H01L2924/00014 , H01L2924/01029 , H01L2924/13055 , H01L2924/13091 , H01L2924/19107 , H01L2924/00 , H01L2224/45015 , H01L2924/207
Abstract: A method includes providing a subassembly having a circuit carrier with a first metallic surface portion, a first joining partner, which is integrally connected to the first metallic surface portion by means of a first connecting layer, and a second metallic surface portion. In a heat treatment, the second metallic surface portion is held uninterruptedly at temperatures which are higher than a minimum heat-treatment temperature of at least 300° C. Moreover, a second joining partner is provided. A fixed connection is produced between the second joining partner and the subassembly in that the second joining partner is integrally connected to the subassembly following completion of the heat treatment on the second surface portion.
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