公开(公告)号：US20170207908A1

公开(公告)日：2017-07-20

申请号：US15375059

申请日：2016-12-09

Applicant: INPHI CORPORATION

Inventor： Halil CIRIT ,  Karthik GOPALAKRISHNAN ,  Pulkit KHANDELWAL ,  Ravindran MOHANAVELU

IPC: H04L7/033 ,  H04L5/00

CPC classification number: H04L7/0332 ,  H03L7/00 ,  H03L7/0807 ,  H04L5/0048 ,  H04L7/033 ,  H04L25/14 ,  H04L27/02 ,  H04Q2213/03

Abstract: The present invention is directed to communication systems. According to embodiments of the present invention, a communication system includes at least two communication lanes and a skew management module. The skew management module generates a control current based on output test patterns of the two communication lanes. The control current is integrated and compared to a reference voltage by a comparator, which generates an analog offset signal. A PLL of one of the communication lanes generates a corrected clock signal that is adjusted using the analog offset signal to remove or adjust the skew between the communication lanes. The corrected clock signal is used for output data. There are other embodiments as well.

公开(公告)号：US20200099453A1

公开(公告)日：2020-03-26

申请号：US16696913

申请日：2019-11-26

Applicant: INPHI CORPORATION

Inventor： Karthik GOPALAKRISHNAN ,  Jamal RIANI ,  Arun TIRUVUR

IPC: H04B10/40 ,  H03K5/00 ,  H03K19/0185 ,  H03L7/093 ,  H03L7/099 ,  H03L7/197 ,  H03L7/23 ,  H04L7/00 ,  H04L25/00 ,  H04L25/49 ,  H04B10/54 ,  H04L7/033

Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

公开(公告)号：US20170201267A1

公开(公告)日：2017-07-13

申请号：US15426506

申请日：2017-02-07

Applicant: INPHI CORPORATION

Inventor： Michael LE ,  James GORECKI ,  Jamal RIANI ,  Jorge PERNILLO ,  Amber TAN ,  Karthik GOPALAKRISHNAN ,  Belal HELAL ,  Chang-Feng LOI ,  Irene QUEK ,  Guojun REN

IPC: H03M1/38 ,  H03M1/12 ,  H03L7/10 ,  H04L25/03

CPC classification number: H03M1/38 ,  H03M1/0604 ,  H03M1/1038 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/1245 ,  H03M1/468 ,  H04L25/03012 ,  H04L25/03019 ,  H04L25/03878

Abstract: In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.

公开(公告)号：US20210167858A1

公开(公告)日：2021-06-03

申请号：US17171801

申请日：2021-02-09

Applicant: INPHI CORPORATION

Inventor： Karthik GOPALAKRISHNAN ,  Jamal RIANI ,  Arun TIRUVUR

IPC: H04B10/40 ,  H03K5/00 ,  H03K19/0185 ,  H03L7/093 ,  H03L7/099 ,  H03L7/197 ,  H03L7/23 ,  H04L7/00 ,  H04L25/00 ,  H04L25/49 ,  H04B10/54 ,  H04L7/033

Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

公开(公告)号：US20190149238A1

公开(公告)日：2019-05-16

申请号：US16249642

申请日：2019-01-16

Applicant: INPHI CORPORATION

Inventor： Karthik GOPALAKRISHNAN ,  Jamal RIANI ,  Arun TIRUVUR

IPC: H04B10/40 ,  H04L25/00 ,  H04L25/49 ,  H04L7/033 ,  H04L7/00 ,  H03L7/23 ,  H03L7/197 ,  H03L7/099 ,  H03L7/093 ,  H03K19/0185 ,  H03K5/00 ,  H04B10/54

CPC classification number: H04B10/40 ,  H03K5/00 ,  H03K19/018521 ,  H03L7/093 ,  H03L7/099 ,  H03L7/1976 ,  H03L7/23 ,  H03L2207/06 ,  H04B10/541 ,  H04L7/0037 ,  H04L7/0062 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/0091 ,  H04L7/0331 ,  H04L25/00 ,  H04L25/49

Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.