APPARATUS AND METHOD FOR COMMUNICATING DATA OVER A COMMUNICATION CHANNEL

    公开(公告)号:US20200014407A1

    公开(公告)日:2020-01-09

    申请号:US16575236

    申请日:2019-09-18

    Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.

    SOFT FEC WITH PARITY CHECK
    4.
    发明申请

    公开(公告)号:US20200343999A1

    公开(公告)日:2020-10-29

    申请号:US16928821

    申请日:2020-07-14

    Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.

    SOFT FEC WITH PARITY CHECK
    5.
    发明申请

    公开(公告)号:US20200220659A1

    公开(公告)日:2020-07-09

    申请号:US16824261

    申请日:2020-03-19

    Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that processes an interleaved data stream and generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.

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