RETIMER DATA COMMUNICATION MODULES
    1.
    发明申请

    公开(公告)号:US20200244561A1

    公开(公告)日:2020-07-30

    申请号:US16848597

    申请日:2020-04-14

    Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide a retimer module that includes plurality of communication lanes for interfacing with a host system and a line system. The retimer module includes a link monitor and cross point sections. The retimer also includes a management interface module. There are other embodiments as well.

    PULSE AMPLITUDE MODULATION (PAM) DATA COMMUNICATION WITH FORWARD ERROR CORRECTION

    公开(公告)号:US20170187555A1

    公开(公告)日:2017-06-29

    申请号:US15405020

    申请日:2017-01-12

    CPC classification number: H04L27/04 H04L1/0041 H04L1/0042 H04L1/0045 H04L25/14

    Abstract: The present invention is directed to data communication system and methods. More specifically, embodiments of the present invention provide an apparatus that receives data from multiple lanes, which are then synchronized for transcoding and encoding. A pseudo random bit sequence checker may be coupled to each of the plurality of lanes, which is configured to a first clock signal A. Additionally, an apparatus may include a plurality of skew compensator modules. Each of the skew compensator modules may be coupled to at least one of the plurality of lanes. The skew-compensator modules are configured to synchronize data from the plurality of lanes. The apparatus additionally includes a plurality of de-skew FIFO modules. Each of the de-skew compensator modules may be coupled to at least one of the plurality of skew compensator modules.

    FORWARD ERROR CORRECTION (FEC) EMULATOR

    公开(公告)号:US20180123613A1

    公开(公告)日:2018-05-03

    申请号:US15337136

    申请日:2016-10-28

    CPC classification number: H03M13/015 H03M13/1515 H03M13/158

    Abstract: Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GF10 Reed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).

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