公开(公告)号：US20160216916A1

公开(公告)日：2016-07-28

申请号：US14923345

申请日：2015-10-26

Applicant: INPHI CORPORATION

Inventor： Christopher HAYWOOD ,  David WANG

IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10

CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0778 ,  G06F11/0787 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G11C5/04 ,  G11C7/1006 ,  G11C29/52 ,  G11C2029/0411

Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

公开(公告)号：US20140269139A1

公开(公告)日：2014-09-18

申请号：US14175857

申请日：2014-02-07

Applicant: INPHI CORPORATION

Inventor： David WANG

IPC: G11C11/4063

CPC classification number: G11C11/4063 ,  G11C11/40611 ,  G11C11/4076

Abstract: In an example, the present invention provides a computing system. The system has a memory interface device comprising a counter, a dynamic random access memory device coupled to the memory interface device. The device comprises a plurality of banks, each of the banks having a subarray, each subarray having a plurality of memory cells. The device has a data interface coupled to the plurality of banks. The device has an address interface coupled to the plurality of banks, and a particular pre-charge command configured to be transferred to the memory interface device. The counter is adapted to count a measured time duration from a first time when data are available at the data interface to a second time when a pre-charge command is received by the address interface.

Abstract translation: 在一个示例中，本发明提供一种计算系统。 该系统具有包括计数器，耦合到存储器接口设备的动态随机存取存储器设备的存储器接口设备。 该设备包括多个存储体，每个存储体具有子阵列，每个子阵列具有多个存储单元。 该设备具有耦合到多个存储体的数据接口。 该设备具有耦合到多个存储区的地址接口，以及被配置为传送到存储器接口设备的特定预充电命令。 该计数器适于对数据接口上的数据可用的第一次计数到第二次当地址接口接收到预充电命令时的测量持续时间。

公开(公告)号：US20160110136A1

公开(公告)日：2016-04-21

申请号：US14975273

申请日：2015-12-18

Applicant: INPHI CORPORATION

Inventor： Nirmal Raj SAXENA ,  Sreenivas KRISHNAN ,  David WANG

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/0644 ,  G06F3/0658 ,  G06F3/067 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0813 ,  G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

Abstract: Techniques for a massively parallel and memory centric computing system. The system has a plurality of processing units operably coupled to each other through one or more communication channels. Each of the plurality of processing units has an ISMn interface device. Each of the plurality of ISMn interface devices is coupled to an ISMe endpoint connected to each of the processing units. The system has a plurality of DRAM or Flash memories configured in a disaggregated architecture and one or more switch nodes operably coupling the plurality of DRAM or Flash memories in the disaggregated architecture. The system has a plurality of high speed optical cables configured to communicate at a transmission rate of 100 G or greater to facilitate communication from any one of the plurality of processing units to any one of the plurality of DRAM or Flash memories.

Abstract translation: 大规模并行和以内存为中心的计算系统的技术。 该系统具有通过一个或多个通信信道彼此可操作地耦合的多个处理单元。 多个处理单元中的每一个具有ISMn接口装置。 多个ISMn接口设备中的每一个耦合到连接到每个处理单元的ISMe端点。 该系统具有以分解体系结构配置的多个DRAM或闪存，以及可操作地以分解结构耦合多个DRAM或闪速存储器的一个或多个交换节点。 该系统具有多个高速光缆，其配置为以100G或更大的传输速率进行通信，以便于从多个处理单元中的任何一个到多个DRAM或闪存中的任何一个的通信。

公开(公告)号：US20150121133A1

公开(公告)日：2015-04-30

申请号：US14593257

申请日：2015-01-09

Applicant: INPHI CORPORATION

Inventor： David WANG

IPC: G06F11/10 ,  G06F11/00

CPC classification number: G06F11/1076 ,  G06F11/008 ,  G06F11/1004 ,  G06F11/1016 ,  G06F12/00

Abstract: A buffer integrated circuit device. The device comprising an output driver formed on the substrate member, the output driver having at least a command bus and an address bus. The device has a protocol and parity checking block (“Block”). The device has a table configured in the block. The table is programmable with a plurality of timing parameters. The device has a memory state block coupled to the table and a command history table coupled to the table to process protocol information for all commands that pass through the Block. The buffer integrated circuit device utilizes the protocol checking functionality to prevent failure propagation and enables data protection even in the case of host memory controller failure or system-level failure of any signal or signals on the command, control and address bus from the host memory controller to the buffer integrated device.

Abstract translation: 缓冲器集成电路器件。 所述装置包括形成在所述衬底构件上的输出驱动器，所述输出驱动器至少具有命令总线和地址总线。 该设备具有协议和奇偶校验块（“块”）。 该设备具有在该块中配置的表。 该表可以用多个定时参数来编程。 该设备具有耦合到该表的存储器状态块和耦合到该表的命令历史表，以处理通过该块的所有命令的协议信息。 缓冲器集成电路器件利用协议检查功能来防止故障传播，并且即使在主机存储器控制器故障或者来自主机存储器控制器的命令，控制和地址总线上的任何信号或信号的系统级故障的情况下也能够进行数据保护 到缓冲器集成器件。

公开(公告)号：US20130262956A1

公开(公告)日：2013-10-03

申请号：US13791124

申请日：2013-03-08

Applicant: INPHI CORPORATION

Inventor： Christopher HAYWOOD ,  David WANG

IPC: G06F11/10 ,  G11C7/10

CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0778 ,  G06F11/0787 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G11C5/04 ,  G11C7/1006 ,  G11C29/52 ,  G11C2029/0411

Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

Abstract translation: 一种用于操作DRAM设备的方法。 该方法包括在由计算系统托管的第一存储器模块中的存储器缓冲器中接收从计算系统的主机控制器存储在第一存储器模块的RAM中的数据的请求。 该方法包括响应于该请求而与RAM相关联的数据与存储缓冲器一起接收，响应于伪随机过程将该数据转换成加扰数据。 该方法包括利用存储缓冲器启动加扰数据到接口设备中。