公开(公告)号：US20150103481A1

公开(公告)日：2015-04-16

申请号：US14576008

申请日：2014-12-18

Applicant: INPHI CORPORATION

Inventor： Christopher HAYWOOD ,  Chao XU ,  Fouad G. TAMER

IPC: H05K7/14 ,  H05K7/20

CPC classification number: G06F13/28 ,  G06F13/4027 ,  G06F13/4282 ,  G11C8/00 ,  H05K7/1487 ,  H05K7/1488 ,  H05K7/1489 ,  H05K7/1491 ,  H05K7/1492 ,  H05K7/20836 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention is directed to server systems and methods thereof. More specifically, embodiments of the present invention provides a memory controller within a server system, where the memory controller is disengageably connected to one or more processors, a plurality of volatile memory modules, and plurality of solid-state memory modules. This memory controller may be connected to other similarly configured memory controllers. The volatile and solid-state memory modules can be removed and/or replaced. There are other embodiments as well.

Abstract translation: 本发明涉及服务器系统及其方法。 更具体地，本发明的实施例提供了服务器系统内的存储器控​​制器，其中存储器控制器可分离地连接到一个或多个处理器，多个易失性存储器模块和多个固态存储器模块。 该存储器控制器可以连接到其他类似配置的存储器控​​制器。 可以移除和/或更换易失性和固态存储器模块。 还有其它实施例。

公开(公告)号：US20160026601A1

公开(公告)日：2016-01-28

申请号：US14878680

申请日：2015-10-08

Applicant: INPHI CORPORATION

Inventor： Christopher HAYWOOD ,  Chao XU ,  Fouad G. TAMER

IPC: G06F13/42 ,  H05K7/20 ,  H05K7/14

CPC classification number: G06F13/28 ,  G06F13/4027 ,  G06F13/4282 ,  G11C8/00 ,  H05K7/1487 ,  H05K7/1488 ,  H05K7/1489 ,  H05K7/1491 ,  H05K7/1492 ,  H05K7/20836 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention is directed to server systems and methods thereof. More specifically, embodiments of the present invention provides a memory controller within a server system, where the memory controller is disengageably connected to one or more processors, a plurality of volatile memory modules, and plurality of solid-state memory modules. This memory controller may be connected to other similarly configured memory controllers. The volatile and solid-state memory modules can be removed and/or replaced. There are other embodiments as well.

公开(公告)号：US20130262956A1

公开(公告)日：2013-10-03

申请号：US13791124

申请日：2013-03-08

Applicant: INPHI CORPORATION

Inventor： Christopher HAYWOOD ,  David WANG

IPC: G06F11/10 ,  G11C7/10

CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0778 ,  G06F11/0787 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G11C5/04 ,  G11C7/1006 ,  G11C29/52 ,  G11C2029/0411

Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

Abstract translation: 一种用于操作DRAM设备的方法。 该方法包括在由计算系统托管的第一存储器模块中的存储器缓冲器中接收从计算系统的主机控制器存储在第一存储器模块的RAM中的数据的请求。 该方法包括响应于该请求而与RAM相关联的数据与存储缓冲器一起接收，响应于伪随机过程将该数据转换成加扰数据。 该方法包括利用存储缓冲器启动加扰数据到接口设备中。

公开(公告)号：US20160216916A1

公开(公告)日：2016-07-28

申请号：US14923345

申请日：2015-10-26

Applicant: INPHI CORPORATION

Inventor： Christopher HAYWOOD ,  David WANG

IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10

CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0778 ,  G06F11/0787 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G11C5/04 ,  G11C7/1006 ,  G11C29/52 ,  G11C2029/0411

Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

公开(公告)号：US20160239240A1

公开(公告)日：2016-08-18

申请号：US15137467

申请日：2016-04-25

Applicant: INPHI CORPORATION

Inventor： Shih-ho WU ,  Christopher HAYWOOD

IPC: G06F3/06 ,  G06F11/16 ,  G11C14/00

CPC classification number: G06F3/0647 ,  G06F3/0619 ,  G06F3/0683 ,  G06F3/0688 ,  G06F11/1441 ,  G06F11/1458 ,  G06F11/1469 ,  G06F11/1662 ,  G06F11/1666 ,  G06F11/2015 ,  G06F12/0246 ,  G06F12/0868 ,  G06F2201/83 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7209 ,  G11C14/0009 ,  Y02D10/13

Abstract: The present invention is directed to computer storage systems and methods thereof. More specifically, embodiments of the present invention provide an isolated storage control system that includes both a non-volatile memory and a volatile memory. The non-volatile memory comprises a data area and a metadata area. In power failure or similar situations, content of the volatile memory is copied to the data area of the non-volatile memory, and various system parameters are stored at the metadata area. When the system restores its operation, the information at the metadata area is processed, and the content stored at the data area of the non-volatile memory is copied to the volatile memory. There are other embodiments as well.

Abstract translation: 本发明涉及计算机存储系统及其方法。 更具体地，本发明的实施例提供了一种包括非易失性存储器和易失性存储器的隔离存储控制系统。 非易失性存储器包括数据区域和元数据区域。 在电源故障或类似情况下，易失性存储器的内容被复制到非易失性存储器的数据区域，各种系统参数存储在元数据区域。 当系统恢复其操作时，处理元数据区域处的信息，将存储在非易失性存储器的数据区域的内容复制到易失性存储器。 还有其它实施例。

公开(公告)号：US20160196224A1

公开(公告)日：2016-07-07

申请号：US15073947

申请日：2016-03-18

Applicant: INPHI CORPORATION

Inventor： Christopher HAYWOOD ,  Chao XU ,  Fouad G. TAMER

IPC: G06F13/28 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F13/4027 ,  G06F13/4282 ,  G11C8/00 ,  H05K7/1487 ,  H05K7/1488 ,  H05K7/1489 ,  H05K7/1491 ,  H05K7/1492 ,  H05K7/20836 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention is directed to server systems and methods thereof. More specifically, embodiments of the present invention provides a memory controller within a server system, where the memory controller is disengageably connected to one or more processors, a plurality of volatile memory modules, and plurality of solid-state memory modules. This memory controller may be connected to other similarly configured memory controllers. The volatile and solid-state memory modules can be removed and/or replaced. There are other embodiments as well.