公开(公告)号：US20240248862A1

公开(公告)日：2024-07-25

申请号：US18424010

申请日：2024-01-26

Applicant: INTEL CORPORATION

Inventor： Eliezer WEISSMANN ,  Efraim ROTEM ,  Doron RAJWAN ,  Hisham ABU SALAH ,  Ariel GUR ,  Guy M. THERIEN ,  Russell J. FENGER

IPC: G06F13/24 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30 ,  G06F9/44 ,  G06F9/4401

CPC classification number: G06F13/24 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/44 ,  G06F9/4411

Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

公开(公告)号：US20220179808A1

公开(公告)日：2022-06-09

申请号：US17527929

申请日：2021-11-16

Applicant: INTEL CORPORATION

Inventor： Eliezer WEISSMANN ,  Efraim ROTEM ,  Doron RAJWAN ,  Hisham ABU SALAH ,  Ariel GUR ,  Guy M. THERIEN ,  Russell J. FENGER

IPC: G06F13/24 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30 ,  G06F1/3234 ,  G06F9/44

Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.