公开(公告)号：US20240248862A1

公开(公告)日：2024-07-25

申请号：US18424010

申请日：2024-01-26

Applicant: INTEL CORPORATION

Inventor： Eliezer WEISSMANN ,  Efraim ROTEM ,  Doron RAJWAN ,  Hisham ABU SALAH ,  Ariel GUR ,  Guy M. THERIEN ,  Russell J. FENGER

IPC: G06F13/24 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30 ,  G06F9/44 ,  G06F9/4401

CPC classification number: G06F13/24 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/44 ,  G06F9/4411

Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

公开(公告)号：US20170177415A1

公开(公告)日：2017-06-22

申请号：US14978182

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Vijay DHANRAJ ,  Gaurav KHANNA ,  Russell J. FENGER ,  Monica GUPTA

IPC: G06F9/50 ,  G06F9/455

CPC classification number: G06F9/4881 ,  G06F9/45558 ,  G06F9/5038 ,  G06F9/5044 ,  G06F9/5077 ,  G06F2009/4557 ,  G06F2009/45591

Abstract: Apparatuses, methods and storage medium associated with scheduling of threads and/or virtual machines, are disclosed herein. In embodiments, an apparatus is provided with a scheduler of an operating system and/or a virtual machine monitor. The scheduler is to retrieve or receive capabilities of the cores of one or more multi-core processors of the apparatus with diverse capabilities, and schedule a plurality of threads for execution on selected one or ones of the cores, based at least in part on the capabilities of the cores and characteristics of the plurality of threads. The virtual machine monitor is to retrieve or receive capabilities of the cores, and schedule a plurality of virtual machines for execution on selected one or ones of the cores, based at least in part on the capabilities of the cores and respective priorities of the virtual machines. Other embodiments may be described and/or claimed.

公开(公告)号：US20220179808A1

公开(公告)日：2022-06-09

申请号：US17527929

申请日：2021-11-16

Applicant: INTEL CORPORATION

Inventor： Eliezer WEISSMANN ,  Efraim ROTEM ,  Doron RAJWAN ,  Hisham ABU SALAH ,  Ariel GUR ,  Guy M. THERIEN ,  Russell J. FENGER

IPC: G06F13/24 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30 ,  G06F1/3234 ,  G06F9/44

Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.