公开(公告)号：US20240248862A1

公开(公告)日：2024-07-25

申请号：US18424010

申请日：2024-01-26

Applicant: INTEL CORPORATION

Inventor： Eliezer WEISSMANN ,  Efraim ROTEM ,  Doron RAJWAN ,  Hisham ABU SALAH ,  Ariel GUR ,  Guy M. THERIEN ,  Russell J. FENGER

IPC: G06F13/24 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30 ,  G06F9/44 ,  G06F9/4401

CPC classification number: G06F13/24 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/44 ,  G06F9/4411

Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

公开(公告)号：US20210034107A1

公开(公告)日：2021-02-04

申请号：US15777559

申请日：2015-12-26

Applicant: INTEL CORPORATION

Inventor： Guy M. THERIEN ,  David W. BROWNING ,  Joshua L. ZUNIGA

IPC: G06F1/16 ,  G06F3/14

Abstract: Embodiments are generally directed to a flexible overlapping display. An embodiment of a mobile device includes a processor to process data for the mobile device, a bendable and foldable display screen one or more device sensors to sense an orientation of the mobile device, and one or more display sensors to sense a current arrangement of the display screen. The processor is to identify one or more portions of the display screen that are visible to a user based at least in part on data from the one or more device sensors and the one or more display sensors.

公开(公告)号：US20220179808A1

公开(公告)日：2022-06-09

申请号：US17527929

申请日：2021-11-16

Applicant: INTEL CORPORATION

Inventor： Eliezer WEISSMANN ,  Efraim ROTEM ,  Doron RAJWAN ,  Hisham ABU SALAH ,  Ariel GUR ,  Guy M. THERIEN ,  Russell J. FENGER

IPC: G06F13/24 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30 ,  G06F1/3234 ,  G06F9/44

Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

公开(公告)号：US20170206118A1

公开(公告)日：2017-07-20

申请号：US14997032

申请日：2016-01-15

Applicant: Intel Corporation

Inventor： Guy M. THERIEN ,  Michael D. POWELL ,  Venkatesh RAMANI ,  Arijit BISWAS ,  Guy G. SOTOMAYOR

IPC: G06F9/50 ,  G06F9/30 ,  G06F1/32

CPC classification number: G06F9/5083 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/3009 ,  G06F9/5033 ,  G06F9/5044

Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.