公开(公告)号：US20150185808A1

公开(公告)日：2015-07-02

申请号：US14142791

申请日：2013-12-28

Applicant: INTEL CORPORATION

Inventor： Robert E. GOUGH ,  Mazen G. GEDEON ,  Barnes COOPER ,  Basavaraj B. ASTEKAR ,  Sean C. DARDIS

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3231 ,  G06F1/3253 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D10/173 ,  Y02D50/20

Abstract: An electronic device may be provided that includes a first controller, a second controller, and a bus to connect between the first controller and the second controller. The electronic device may also include a first signal line between the first controller and the second controller, and the first controller to provide a first signal on the first signal line to the second controller to wake up the second controller from a low power mode.

Abstract translation: 可以提供一种电子设备，其包括第一控制器，第二控制器和总线以在第一控制器和第二控制器之间连接。 电子设备还可以包括在第一控制器和第二控制器之间的第一信号线，以及第一控制器，以在第一信号线上向第二控制器提供第一信号，以将第二控制器从低功率模式唤醒。

公开(公告)号：US20180046240A1

公开(公告)日：2018-02-15

申请号：US15634805

申请日：2017-06-27

Applicant: INTEL CORPORATION

Inventor： Robert E. GOUGH ,  Mazen G. GEDEON ,  Barnes COOPER ,  Basavaraj B. ASTEKAR ,  Sean C. DARDIS

IPC: G06F1/32

Abstract: An electronic device may be provided that includes a first controller, a second controller, and a bus to connect between the first controller and the second controller. The electronic device may also include a first signal line between the first controller and the second controller, and the first controller to provide a first signal on the first signal line to the second controller to wake up the second controller from a low power mode.

公开(公告)号：US20170109174A1

公开(公告)日：2017-04-20

申请号：US15394922

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Nathaniel L. DESIMONE ,  Robert E. GOUGH ,  Sean C. DARDIS

IPC: G06F9/44 ,  G06F13/42 ,  G06F13/38

CPC classification number: G06F9/4411 ,  G06F9/4406 ,  G06F13/382 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4221 ,  G06F13/4282

Abstract: Techniques for adaptive interface support are described. In one embodiment, for example, an apparatus may comprise logic, at least a portion of which is in hardware, the logic to execute a basic input/output system (BIOS), determine a respective impedance state for each of one or more pins in an M.2 physical interface, determine an interface type for a peripheral device coupled with the M.2 physical interface based on the impedance states for the one or more pins, and control an operational state of the peripheral device during execution of the BIOS, based on the interface type for the peripheral device. Other embodiments are described and claimed.