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    METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO OPTIMIZE AN I/O SYSTEM
    4.
    发明申请
    METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO OPTIMIZE AN I/O SYSTEM 审中-公开
    用于动态调整电压参考以优化I / O系统的方法和装置

    公开(公告)号：US20160232962A1

    公开(公告)日：2016-08-11

    申请号：US15087963

    申请日：2016-03-31

    Applicant: INTEL CORPORATION

    Inventor： Christopher P. Mozak ,  Kevin B. Moore ,  John V. Lovelace ,  Theodore Z. Schoenborn ,  Bryan L. Spry ,  Christopher E. Yunker

    IPC: G11C11/4091 ,  G11C11/4093 ,  G11C11/4099

    CPC classification number: G11C11/4091 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4099

    Abstract: Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

    Abstract translation: 这里描述了一种用于动态调整电压参考电平以便优化I / O系统以实现某一性能度量的装置。 该装置包括：电压基准发生器，用于产生电压基准; 以及与电压参考发生器耦合的动态电压参考控制单元，以响应于事件来动态地调整电压参考电平。 该装置用于执行该方法，包括：产生用于输入/输出（I / O）系统的电压基准; 确定电压基准的最坏情况电压电平; 基于确定最坏情况电压电平，通过动态电压基准控制单元动态调整电压参考电平; 以及基于动态调整的电压参考电平计算不对称眼睛的中心。

    Method, apparatus and system for configuring a protocol stack of an integrated circuit chip
    5.
    发明授权
    Method, apparatus and system for configuring a protocol stack of an integrated circuit chip 有权

    公开(公告)号：US10282341B2

    公开(公告)日：2019-05-07

    申请号：US15671900

    申请日：2017-08-08

    Applicant: Intel Corporation

    Inventor： Bryan L. Spry ,  Marcus W. Song ,  Deepak M. Rangaraj ,  Avinash N. Ananthakrishnan ,  Robert J. Hayes ,  Aimee D. Wood ,  Adam E. Letendre ,  Brent R. Boswell

    IPC: G06F13/20 ,  G06F13/42 ,  G06F13/12

    Abstract: Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.

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