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    Memory bus MR register programming process
    1.
    发明授权
    Memory bus MR register programming process 有权

    公开(公告)号：US10891243B2

    公开(公告)日：2021-01-12

    申请号：US16529700

    申请日：2019-08-01

    Applicant: Intel Corporation

    Inventor： Tonia G. Morris ,  John V. Lovelace ,  John R. Goles

    IPC: G06F13/36 ,  G06F13/16 ,  G06F1/10

    Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

    Fast boot up memory controller
    3.
    发明授权
    Fast boot up memory controller 有权

    公开(公告)号：US10552643B2

    公开(公告)日：2020-02-04

    申请号：US15392912

    申请日：2016-12-28

    Applicant: INTEL CORPORATION

    Inventor： John V. Lovelace ,  Sreenivas Mandava ,  Debaleena Das

    IPC: G06F21/79

    Abstract: A method performed by a memory controller is described. The method includes, during boot up, issuing a command to a memory to cause the memory to zero out its content. The method also includes bypassing a descrambler when reading from a location in the memory that has not had its zeroed out content written over the scrambled data. The method also includes processing read data with the descrambler when reading from a location in the memory that has had its zeroed out content written over with scrambled data.

    TECHNOLOGIES FOR REDUCED CONTROL AND STATUS REGISTER ACCESS LATENCY
    4.
    发明申请
    TECHNOLOGIES FOR REDUCED CONTROL AND STATUS REGISTER ACCESS LATENCY 审中-公开

    公开(公告)号：US20180095889A1

    公开(公告)日：2018-04-05

    申请号：US15283318

    申请日：2016-10-01

    Applicant: Intel Corporation

    Inventor： Xueyan Wang ,  Wenjuan Mao ,  Qiang Li ,  John V. Lovelace ,  James R. Goffena

    IPC: G06F12/0895 ,  G06F12/0875 ,  G06F12/10 ,  G06F9/445

    CPC classification number: G06F9/44505 ,  G06F12/0875 ,  G06F13/00 ,  G06F2212/452

    Abstract: Technologies for control and status register (CSR) access include a computing device that starts a firmware initialization phase. The firmware accesses a CSR at an abstract CSR address. The computing device determines whether an upper part of the CSR address matches a cached upper part of a previously accessed CSR address. If the upper parts do not match, the computing device converts the CSR address into a physical address and caches the upper part of the CSR address and the upper part of the physical address. If the upper parts match, the computing device combines a cached upper part of a previously accessed physical address with an offset of the CSR address. The upper part may include 20 bits and the lower part may include 12 bits. The physical address may be a PCIe address of the CSR added with an MMCFG base address. Other embodiments are described and claimed.

    Memory bus MR register programming process
    6.
    发明授权
    Memory bus MR register programming process 有权

    公开(公告)号：US10380043B2

    公开(公告)日：2019-08-13

    申请号：US15718346

    申请日：2017-09-28

    Applicant: Intel Corporation

    Inventor： Tonia G. Morris ,  John V. Lovelace ,  John R. Goles

    IPC: G06F13/36 ,  G06F13/16 ,  G06F1/10

    Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

    Technologies for reduced control and status register access latency
    7.
    发明授权
    Technologies for reduced control and status register access latency 有权

    公开(公告)号：US10289431B2

    公开(公告)日：2019-05-14

    申请号：US15283318

    申请日：2016-10-01

    Applicant: Intel Corporation

    Inventor： Xueyan Wang ,  Wenjuan Mao ,  Qiang Li ,  John V. Lovelace ,  James R. Goffena

    IPC: G06F9/445 ,  G06F13/00 ,  G06F12/0875

    Abstract: Technologies for control and status register (CSR) access include a computing device that starts a firmware initialization phase. The firmware accesses a CSR at an abstract CSR address. The computing device determines whether an upper part of the CSR address matches a cached upper part of a previously accessed CSR address. If the upper parts do not match, the computing device converts the CSR address into a physical address and caches the upper part of the CSR address and the upper part of the physical address. If the upper parts match, the computing device combines a cached upper part of a previously accessed physical address with an offset of the CSR address. The upper part may include 20 bits and the lower part may include 12 bits. The physical address may be a PCIe address of the CSR added with an MMCFG base address. Other embodiments are described and claimed.

    METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO OPTIMIZE AN I/O SYSTEM
    9.
    发明申请
    METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO OPTIMIZE AN I/O SYSTEM 审中-公开
    用于动态调整电压参考以优化I / O系统的方法和装置

    公开(公告)号：US20160232962A1

    公开(公告)日：2016-08-11

    申请号：US15087963

    申请日：2016-03-31

    Applicant: INTEL CORPORATION

    Inventor： Christopher P. Mozak ,  Kevin B. Moore ,  John V. Lovelace ,  Theodore Z. Schoenborn ,  Bryan L. Spry ,  Christopher E. Yunker

    IPC: G11C11/4091 ,  G11C11/4093 ,  G11C11/4099

    CPC classification number: G11C11/4091 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4099

    Abstract: Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

    Abstract translation: 这里描述了一种用于动态调整电压参考电平以便优化I / O系统以实现某一性能度量的装置。 该装置包括：电压基准发生器，用于产生电压基准; 以及与电压参考发生器耦合的动态电压参考控制单元，以响应于事件来动态地调整电压参考电平。 该装置用于执行该方法，包括：产生用于输入/输出（I / O）系统的电压基准; 确定电压基准的最坏情况电压电平; 基于确定最坏情况电压电平，通过动态电压基准控制单元动态调整电压参考电平; 以及基于动态调整的电压参考电平计算不对称眼睛的中心。

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