公开(公告)号：US11916554B2

公开(公告)日：2024-02-27

申请号：US16716234

申请日：2019-12-16

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  Ralph S. Li ,  Chin Wah Lim ,  Mahmoud Elassal ,  Anant Balakrishnan ,  Isaac Ali

IPC: H03K3/00 ,  G06F11/16 ,  H03K3/017 ,  H03K5/135 ,  H03K5/156 ,  H03L7/081

CPC classification number: H03K3/017 ,  G06F11/1679 ,  H03K5/135 ,  H03K5/1565 ,  H03L7/0816

Abstract: Examples may include techniques for using a sample clock to measure a duty cycle by periodic sampling a target clock signal based on a prime number ratio of a reference clock frequency. The reference clock frequency used to set a measurement cycle time over which the duty cycle is to be measured. A magnitude of a duty cycle error as compared to a programmable target duty cycle is determined based on the measured duty cycle and the duty cycle is adjusted based, at least in part, on the magnitude of the duty cycle error.

公开(公告)号：US10802996B2

公开(公告)日：2020-10-13

申请号：US16546210

申请日：2019-08-20

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  James A. McCall ,  Bryan K. Casper

IPC: G06F13/20 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  H04L25/49 ,  G06F11/10

Abstract: Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.

公开(公告)号：US10079052B2

公开(公告)日：2018-09-18

申请号：US15944755

申请日：2018-04-03

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  Randy B. Osborne ,  Michael Gutzmann ,  James A. McCall

IPC: G11C8/00 ,  G11C11/4093 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F13/1684 ,  G06F13/1689 ,  G11C11/4076 ,  G11C11/4096 ,  Y02D10/14

Abstract: Methods and apparatus related to multiple rank high bandwidth memory are described. In one embodiment, a semiconductor package includes a high bandwidth memory with multiple ranks. Other embodiments are also disclosed and claimed.

公开(公告)号：US09934842B2

公开(公告)日：2018-04-03

申请号：US15351195

申请日：2016-11-14

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  Randy B. Osborne ,  Michael Gutzmann ,  James A. McCall

IPC: G11C8/00 ,  G11C11/4093 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F13/1684 ,  G06F13/1689 ,  G11C11/4076 ,  G11C11/4096

Abstract: Methods and apparatus related to multiple rank high bandwidth memory are described. In one embodiment, a semiconductor package includes a high bandwidth memory with multiple ranks. Other embodiments are also disclosed and claimed.

公开(公告)号：US20160232962A1

公开(公告)日：2016-08-11

申请号：US15087963

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： Christopher P. Mozak ,  Kevin B. Moore ,  John V. Lovelace ,  Theodore Z. Schoenborn ,  Bryan L. Spry ,  Christopher E. Yunker

IPC: G11C11/4091 ,  G11C11/4093 ,  G11C11/4099

CPC classification number: G11C11/4091 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4099

Abstract: Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

Abstract translation: 这里描述了一种用于动态调整电压参考电平以便优化I / O系统以实现某一性能度量的装置。 该装置包括：电压基准发生器，用于产生电压基准; 以及与电压参考发生器耦合的动态电压参考控制单元，以响应于事件来动态地调整电压参考电平。 该装置用于执行该方法，包括：产生用于输入/输出（I / O）系统的电压基准; 确定电压基准的最坏情况电压电平; 基于确定最坏情况电压电平，通过动态电压基准控制单元动态调整电压参考电平; 以及基于动态调整的电压参考电平计算不对称眼睛的中心。

公开(公告)号：US20160188257A1

公开(公告)日：2016-06-30

申请号：US14952324

申请日：2015-11-25

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  Kuljit S. Bains

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0634 ,  G06F3/0673 ,  G06F3/068 ,  G06F11/2094 ,  G06F2201/805 ,  G11C7/1045 ,  G11C7/24 ,  G11C29/025 ,  G11C29/46 ,  G11C29/50012 ,  G11C29/70 ,  G11C29/76 ,  G11C29/83

Abstract: In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation of the memory device. A field in the mode register may hold a value that may indicate whether a command associated with the memory device is disabled. The value may be held in the field until either the memory device is power-cycled or reset. The device processing logic may acquire an instance of the command. The device processing logic may determine whether the command is disabled based on the value held by the mode register. The device processing logic may not execute the instance of the command if the device processing logic determines the command is disabled. If the device processing logic determines the command is not disabled, the device processing logic may execute the instance of the command.

公开(公告)号：US10347319B2

公开(公告)日：2019-07-09

申请号：US15087963

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： Christopher P. Mozak ,  Kevin B. Moore ,  John V. Lovelace ,  Theodore Z. Schoenborn ,  Bryan L. Spry ,  Christopher E. Yunker

IPC: G11C5/14 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4099

Abstract: Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

公开(公告)号：US10324490B2

公开(公告)日：2019-06-18

申请号：US15490860

申请日：2017-04-18

Applicant: Intel Corporation

Inventor： Christopher P. Mozak

IPC: G06F1/04 ,  G06F13/42 ,  G11C27/02 ,  G11C7/22 ,  H04L7/00 ,  H03L7/00

Abstract: A device with an I/O interface includes a replica clock distribution path matched to a clock distribution path of an unmatched receiver circuit. The device can monitor changes in delay in the replica path, and adjust delay in the real clock distribution path in response to the delay changes detected in the replica path. The receiver circuit includes a data path and a clock distribution network in an unmatched configuration. A ring oscillator circuit includes a replica clock distribution network matched to the real clock distribution network. Thus, delay changes detected for the replica clock distribution network indicates a change in delay in the real clock distribution network, which can be compensated accordingly.

公开(公告)号：US20180226118A1

公开(公告)日：2018-08-09

申请号：US15944755

申请日：2018-04-03

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  Randy B. Osborne ,  Michael Gutzmann ,  James A. McCall

IPC: G11C11/4093 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F13/1684 ,  G06F13/1689 ,  G11C11/4076 ,  G11C11/4096

Abstract: Methods and apparatus related to multiple rank high bandwidth memory are described. In one embodiment, a semiconductor package includes a high bandwidth memory with multiple ranks. Other embodiments are also disclosed and claimed.

公开(公告)号：US09740433B2

公开(公告)日：2017-08-22

申请号：US15358524

申请日：2016-11-22

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  Kuljit S. Bains

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G06F11/20 ,  G11C29/00 ,  G11C7/24 ,  G11C29/46 ,  G11C29/50 ,  G11C7/10 ,  G11C29/02

CPC classification number: G06F3/0659 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0634 ,  G06F3/0673 ,  G06F3/068 ,  G06F11/2094 ,  G06F2201/805 ,  G11C7/1045 ,  G11C7/24 ,  G11C29/025 ,  G11C29/46 ,  G11C29/50012 ,  G11C29/70 ,  G11C29/76 ,  G11C29/83

Abstract: In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation of the memory device. A field in the mode register may hold a value that may indicate whether a command associated with the memory device is disabled. The value may be held in the field until either the memory device is power-cycled or reset. The device processing logic may acquire an instance of the command. The device processing logic may determine whether the command is disabled based on the value held by the mode register. The device processing logic may not execute the instance of the command if the device processing logic determines the command is disabled. If the device processing logic determines the command is not disabled, the device processing logic may execute the instance of the command.