公开(公告)号：US11231937B2

公开(公告)日：2022-01-25

申请号：US15792451

申请日：2017-10-24

Applicant: Intel Corporation

Inventor： Choon Gun Por

IPC: G06F9/00 ,  G06F9/4401 ,  G06F11/30 ,  G06F13/38 ,  G06F21/57 ,  G06F21/85

Abstract: A method and system method for communication port management in a device. The method including enabling a set of communication ports in response to power up of the device, detecting connection at a port in the set of communication ports prior to operating system boot of the device, and connecting an external device to an operational component of the device in response to the connection at the port.

公开(公告)号：US10862730B2

公开(公告)日：2020-12-08

申请号：US16144108

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Karthi Vadivelu ,  Choon Gun Por

IPC: G06F13/20 ,  H04L29/06 ,  G06F13/42 ,  G06F13/40 ,  H05K1/02

Abstract: Embodiments may include systems and methods for communication including a plurality of controllers and coordination circuitry, to control communication to or from an interface circuitry. The interface circuitry includes a plurality of pins, where a first group of pins of the plurality of pins is for a first communication protocol, and a second group of pins of the plurality of pins is for a second communication protocol. A first controller is coupled to the interface circuitry through the first group of pins, and a second controller is coupled to the interface circuitry through the second group of pins. The coordination circuitry is to select the first controller or the second controller to control communication to or from the interface circuitry. Other embodiments may be described and/or claimed.

公开(公告)号：US20190044785A1

公开(公告)日：2019-02-07

申请号：US16144108

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Karthi Vadivelu ,  Choon Gun Por

IPC: H04L29/06 ,  H05K1/02 ,  G06F13/40 ,  G06F13/42

Abstract: Embodiments may include systems and methods for communication including a plurality of controllers and coordination circuitry, to control communication to or from an interface circuitry. The interface circuitry includes a plurality of pins, where a first group of pins of the plurality of pins is for a first communication protocol, and a second group of pins of the plurality of pins is for a second communication protocol. A first controller is coupled to the interface circuitry through the first group of pins, and a second controller is coupled to the interface circuitry through the second group of pins. The coordination circuitry is to select the first controller or the second controller to control communication to or from the interface circuitry. Other embodiments may be described and/or claimed.

公开(公告)号：US09329655B2

公开(公告)日：2016-05-03

申请号：US14126612

申请日：2012-12-13

Applicant: Intel Corporation

Inventor： Choon Gun Por ,  Mun Fook Leong

IPC: G06F1/32 ,  G06F1/26 ,  G06F13/40

CPC classification number: G06F1/266 ,  G06F1/3278 ,  G06F13/4072 ,  Y02D10/151 ,  Y02D10/157

Abstract: According to some embodiments, a communication interface 110 may include a biasing circuit 140 and a logic unit 130. The biasing circuit 140 may be configured to provide a bias voltage to a port of the communication interface 110. The logic unit 130 may be configured to enable and disable the biasing circuit 140 based on a first signal received from a controller of the communication interface 110. The logic unit 130 may also be configured to enable and disable the biasing circuit 140 based on a suspend signal received from the controller of the communication interface 110.

Abstract translation: 根据一些实施例，通信接口110可以包括偏置电路140和逻辑单元130.偏置电路140可以被配置为向通信接口110的端口提供偏置电压。逻辑单元130可以被配置为 基于从通信接口110的控制器接收的第一信号来启用和禁用偏置电路140.逻辑单元130还可以被配置为基于从通信的控制器接收的挂起信号来使能和禁用偏置电路140 接口110。

公开(公告)号：US09575552B2

公开(公告)日：2017-02-21

申请号：US14129545

申请日：2013-04-17

Applicant: INTEL CORPORATION

Inventor： Choon Gun Por ,  Su Wei Lim

IPC: G06F13/36 ,  G06F1/32 ,  G06F1/26 ,  G06F13/364 ,  G06F13/42 ,  G06F13/38

CPC classification number: G06F1/3296 ,  G06F1/266 ,  G06F13/364 ,  G06F13/4221 ,  Y02D10/14 ,  Y02D10/151

Abstract: Translation circuitry for facilitating communication between a protocol stack for a PCIe™ communication protocol and a PHY layer for a low power communication standard. In an embodiment, the translation circuitry includes logic is to variously convert signaling between two or more PHY interface standards. The one or more a PHY interface standards may include a PHY Interface for PCI Express (PIPE) specification and a standard for a comparatively low power communication protocol. In another embodiment, the low power communication standard is a Reference M-PHY Module Interface (RMMI) specification.

Abstract translation: 用于促进用于PCIe TM通信协议的协议栈与用于低功率通信标准的PHY层之间的通信的翻译电路。 在一个实施例中，翻译电路包括逻辑是在两个或多个PHY接口标准之间不同地转换信令。 一个或多个PHY接口标准可以包括用于PCI Express（PIPE）规范的PHY接口和用于相对低功率通信协议的标准。 在另一个实施例中，低功率通信标准是参考M-PHY模块接口（RMMI）规范。