公开(公告)号：US20200219789A1

公开(公告)日：2020-07-09

申请号：US16241108

申请日：2019-01-07

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Je-Young Chang ,  Javed Shaikh ,  Divya Mani ,  Weihua Tang

IPC: H01L23/427 ,  H01L23/522 ,  H01L21/48 ,  H01L23/00

Abstract: An integrated circuit structure may be formed using a phase change material to substantially fill at least one chamber within the integrated circuit assembly to increase thermal capacitance. The integrated circuit assembly may comprise a substrate, at least one integrated circuit device electrically attached to the substrate, a heat dissipation device, a thermal interface material between the integrated circuit device and the heat dissipation device, a chamber defined by the heat dissipation device, the substrate, and the integrated circuit device, and a phase change material within the chamber.

公开(公告)号：US11581240B2

公开(公告)日：2023-02-14

申请号：US16230021

申请日：2018-12-21

Applicant: INTEL CORPORATION

Inventor： Kedar Dhane ,  Omkar Karhade ,  Aravindha R. Antoniswamy ,  Divya Mani

IPC: H01L23/34 ,  H01L23/42 ,  H01L23/31 ,  H01L23/00

Abstract: An integrated circuit package that includes a liquid phase thermal interface material (TIM) is described. The package may include any number of die. The liquid phase TIM can be sealed in a chamber between a die and an integrated heat spreader and bounded on the sides by a perimeter layer. The liquid phase TIM can be fixed in place or circulated, depending on application. A thermal conductivity of the liquid phase TIM can be at least 15 Watts/meter-Kelvin, according to some embodiments. A liquid phase TIM eliminates failure mechanisms present in solid phase TIMs, such as cracking due to warpage and uncontained flow out of the module.

公开(公告)号：US11112841B2

公开(公告)日：2021-09-07

申请号：US16481396

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Divya Mani ,  William J. Lambert ,  Shawna Liff ,  Sergio A. Chan Arguedas ,  Robert L. Sankman

IPC: G06F1/20 ,  H05K1/02 ,  H05K1/14 ,  H05K3/00 ,  H01Q23/00 ,  H04B1/40

Abstract: Embodiments of the invention include a mmWave transceiver and methods of forming such devices. In an embodiment, the mmWave transceiver includes an RF module. The RF module may include a package substrate, a plurality of antennas formed on the package substrate, and a die attached to a surface of the package substrate. In an embodiment, the mmWave transceiver may also include a mainboard mounted to the RF module with one or more solder balls. In an embodiment, a thermal feature is embedded within the mainboard, and the thermal feature is separated from the die by a thermal interface material (TIM) layer. According to an embodiment, the thermal features are slugs and/or vias. In an embodiment, the die compresses the TIM layer resulting in a TIM layer with minimal thickness.

公开(公告)号：US11830783B2

公开(公告)日：2023-11-28

申请号：US16600107

申请日：2019-10-11

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Divya Mani ,  Je-Young Chang

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/433 ,  H01L25/00 ,  H01L23/10 ,  H01L21/48 ,  H01L23/373 ,  H01L25/16 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/367 ,  H01L21/4875 ,  H01L23/10 ,  H01L23/3736 ,  H01L23/433 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/165 ,  H01L25/50 ,  H01L23/3128 ,  H01L23/49816

Abstract: Embodiments include semiconductor packages. A semiconductor package include a high-power electronic component and an embedded heat spreader (EHS) in a package substrate. The EHS is adjacent to the high-power electronic component. The semiconductor package includes a plurality of thermal interconnects below the EHS and the package substrate, and a plurality of dies on the package substrate. The thermal interconnects is coupled to the EHS. The EHS is below the high-power electronic component and embedded within the package substrate. The high-power electronic component has a bottom surface substantially proximate to a top surface of the EHS. The EHS is a copper heat sink, and the high-power electronic component is an air core inductor or a voltage regulator. The thermal interconnects are comprised of thermal ball grid array balls or thermal adhesive materials. The thermal interconnects couple a bottom surface of the package substrate to a top surface of a substrate.

公开(公告)号：US11640929B2

公开(公告)日：2023-05-02

申请号：US16227201

申请日：2018-12-20

Applicant: Intel Corporation

Inventor： Nicholas Neal ,  Divya Mani ,  Nicholas Haehn

IPC: H01L23/00 ,  H01L23/473 ,  H01L23/498 ,  H01L23/467 ,  H01L21/48

Abstract: An integrated circuit assembly may be formed having a substrate core, wherein the substrate core includes at least one heat transfer fluid channel formed therein, a first build-up layer formed on a first surface of the substrate core, and a second build-up layer formed on a second surface of the substrate core, and methods of fabricating the same. In embodiments of the present description, the integrated circuit structure may include at least one integrated circuit device formed within at least one of the first build-up layer and the second build-up layer. The embodiments of the present description allow for cooling within the substrate, which may significantly reduce thermal damage to the components of the substrate and/or integrated circuit devices within the substrate.