公开(公告)号：US10672625B2

公开(公告)日：2020-06-02

申请号：US16083611

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Sergio A. Chan Arguedas ,  Joshua D. Heppner ,  Jimin Yao

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/13 ,  H01L23/15 ,  H01L23/14

Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a recess, an electronic component disposed in the recess and electrically coupled to the substrate, and an underfill material disposed in the recess between the electronic component and the substrate. Associated systems and methods are also disclosed.

公开(公告)号：US11112841B2

公开(公告)日：2021-09-07

申请号：US16481396

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Divya Mani ,  William J. Lambert ,  Shawna Liff ,  Sergio A. Chan Arguedas ,  Robert L. Sankman

IPC: G06F1/20 ,  H05K1/02 ,  H05K1/14 ,  H05K3/00 ,  H01Q23/00 ,  H04B1/40

Abstract: Embodiments of the invention include a mmWave transceiver and methods of forming such devices. In an embodiment, the mmWave transceiver includes an RF module. The RF module may include a package substrate, a plurality of antennas formed on the package substrate, and a die attached to a surface of the package substrate. In an embodiment, the mmWave transceiver may also include a mainboard mounted to the RF module with one or more solder balls. In an embodiment, a thermal feature is embedded within the mainboard, and the thermal feature is separated from the die by a thermal interface material (TIM) layer. According to an embodiment, the thermal features are slugs and/or vias. In an embodiment, the die compresses the TIM layer resulting in a TIM layer with minimal thickness.

公开(公告)号：US11832419B2

公开(公告)日：2023-11-28

申请号：US16723865

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Nicholas Neal ,  Nicholas S. Haehn ,  Je-Young Chang ,  Kyle Arrington ,  Aaron McCann ,  Edvin Cetegen ,  Ravindranath V. Mahajan ,  Robert L. Sankman ,  Ken P. Hackenberg ,  Sergio A. Chan Arguedas

IPC: H05K7/20 ,  H01L23/498 ,  H01L23/00 ,  H01L23/367

CPC classification number: H05K7/20309 ,  H01L23/3672 ,  H01L23/49816 ,  H01L24/14

Abstract: Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.

公开(公告)号：US20190074199A1

公开(公告)日：2019-03-07

申请号：US16083611

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Sergio A. Chan Arguedas ,  Joshua D. Heppner ,  Jimin Yao

IPC: H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00

Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a recess, an electronic component disposed in the recess and electrically coupled to the substrate, and an underfill material disposed in the recess between the electronic component and the substrate. Associated systems and methods are also disclosed.