公开(公告)号：US20170093064A1

公开(公告)日：2017-03-30

申请号：US14863974

申请日：2015-09-24

Applicant: INTEL CORPORATION

Inventor： JACKSON CHUNG PENG KONG ,  ENG HUAT GOH ,  BOK ENG CHEAH ,  SU SIN FLORENCE PHUN ,  KHANG CHOONG YONG ,  MIN KEEN TANG

IPC: H01R12/72 ,  C25D7/00 ,  H01G4/228 ,  C25D5/48 ,  H01G4/06 ,  H01R13/66 ,  C25D5/34

CPC classification number: H01R12/721 ,  C23C18/1653 ,  C25D5/34 ,  C25D5/48 ,  C25D7/00 ,  H01G4/06 ,  H01G4/228 ,  H01G4/40 ,  H01R12/732 ,  H01R13/6625 ,  H05K1/117 ,  H05K1/162 ,  H05K3/00 ,  H05K2201/0187

Abstract: A board-edge interconnection module features integrated capacitive coupling, which enables a board design employing the module to avoid having AC capacitors and flexible cables with bulky connectors. The recovered real estate enables further miniaturization, enabling the component to be used on a wide variety of devices, including ultra-mobile computing devices.

公开(公告)号：US20210202441A1

公开(公告)日：2021-07-01

申请号：US16070510

申请日：2016-02-05

Applicant: INTEL CORPORATION

Inventor： ENG HUAT GOH ,  CHU AUN LIM ,  UPENDRA R. SHETH ,  ROBERT STARKSTON

IPC: H01L25/065 ,  H01L23/00

Abstract: Various embodiments are generally directed to an electronic assembly comprising at least two dies stacked on top of each other. Metal columns of different heights electrically connect the dies to a system substrate.

公开(公告)号：US20180286804A1

公开(公告)日：2018-10-04

申请号：US15476905

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： SEOK LING LIM ,  ENG HUAT GOH ,  HOAY TIEN TEOH ,  JENNY SHIO YIN ONG ,  JIA YAN GO ,  JIUN HANN SIR ,  MIN SUET LIM

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5223 ,  H01L23/043 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5222 ,  H01L23/5286 ,  H01L2225/06548 ,  H01L2225/1047

Abstract: Interconnects for semiconductor packages are described. An apparatus may comprise a decoupling capacitor on a logic board, and a conductive interconnect element on the logic board, the conductive interconnect element to connect the decoupling capacitor on the logic board to a power conductor comprising a power pad of a semiconductor package, the conductive interconnect element at a different layer than a ground-potential layer of the logic board. Other embodiments are described and claimed.

公开(公告)号：US20170091131A1

公开(公告)日：2017-03-30

申请号：US14864019

申请日：2015-09-24

Applicant: INTEL CORPORATION

Inventor： KHANG CHOONG YONG ,  KHAI ERN SEE ,  AMIT KUMAR SRIVASTAVA ,  JACKSON CHUNG PENG KONG ,  TEONG KEAT BEH ,  ENG HUAT GOH

IPC: G06F13/38 ,  G06F3/06 ,  G06F11/14 ,  G06F13/40

CPC classification number: G06F13/385 ,  G06F3/0634 ,  G06F3/065 ,  G06F3/0673 ,  G06F11/1456 ,  G06F13/4022 ,  G06F13/4081 ,  G06F2201/84

Abstract: A universal interconnection scheme enables system architecture modularization with a hot-pluggable external computing module, such as a PC-on-a-card device using USB type-C technology. With the flexibility to interchange the system computing module with an external module, system performance can be augmented to fulfill the essential needs of the user, whether the system is a portable low-power tablet device, a smartphone, a wearable device such as an Internet of Things device, or a high-performance PC.