公开(公告)号：US20170093064A1

公开(公告)日：2017-03-30

申请号：US14863974

申请日：2015-09-24

Applicant: INTEL CORPORATION

Inventor： JACKSON CHUNG PENG KONG ,  ENG HUAT GOH ,  BOK ENG CHEAH ,  SU SIN FLORENCE PHUN ,  KHANG CHOONG YONG ,  MIN KEEN TANG

IPC: H01R12/72 ,  C25D7/00 ,  H01G4/228 ,  C25D5/48 ,  H01G4/06 ,  H01R13/66 ,  C25D5/34

CPC classification number: H01R12/721 ,  C23C18/1653 ,  C25D5/34 ,  C25D5/48 ,  C25D7/00 ,  H01G4/06 ,  H01G4/228 ,  H01G4/40 ,  H01R12/732 ,  H01R13/6625 ,  H05K1/117 ,  H05K1/162 ,  H05K3/00 ,  H05K2201/0187

Abstract: A board-edge interconnection module features integrated capacitive coupling, which enables a board design employing the module to avoid having AC capacitors and flexible cables with bulky connectors. The recovered real estate enables further miniaturization, enabling the component to be used on a wide variety of devices, including ultra-mobile computing devices.

公开(公告)号：US20170091131A1

公开(公告)日：2017-03-30

申请号：US14864019

申请日：2015-09-24

Applicant: INTEL CORPORATION

Inventor： KHANG CHOONG YONG ,  KHAI ERN SEE ,  AMIT KUMAR SRIVASTAVA ,  JACKSON CHUNG PENG KONG ,  TEONG KEAT BEH ,  ENG HUAT GOH

IPC: G06F13/38 ,  G06F3/06 ,  G06F11/14 ,  G06F13/40

CPC classification number: G06F13/385 ,  G06F3/0634 ,  G06F3/065 ,  G06F3/0673 ,  G06F11/1456 ,  G06F13/4022 ,  G06F13/4081 ,  G06F2201/84

Abstract: A universal interconnection scheme enables system architecture modularization with a hot-pluggable external computing module, such as a PC-on-a-card device using USB type-C technology. With the flexibility to interchange the system computing module with an external module, system performance can be augmented to fulfill the essential needs of the user, whether the system is a portable low-power tablet device, a smartphone, a wearable device such as an Internet of Things device, or a high-performance PC.

公开(公告)号：US20160092392A1

公开(公告)日：2016-03-31

申请号：US14499109

申请日：2014-09-27

Applicant: Intel Corporation

Inventor： KHANG CHOONG YONG ,  WIL CHOON SONG ,  HOWARD L. HECK

IPC: G06F13/40 ,  G06F11/30 ,  G06F11/22

CPC classification number: G06F13/4086 ,  G06F11/221 ,  G06F11/3027 ,  Y02D10/14 ,  Y02D10/151

Abstract: Methods and apparatus relating to an adaptive termination scheme for a low power, high speed bus are described. In an embodiment, logic at least partially causes termination of a portion (e.g., one or more transmission lines) of an interconnect. The logic adaptively optimizes the number of lines that are to be terminated based on one or more operating conditions of the interconnect. Other embodiments are also disclosed.

Abstract translation: 描述与低功率，高速总线的自适应终端方案有关的方法和装置。 在一个实施例中，逻辑至少部分地导致互连的一部分（例如一个或多个传输线）的终止。 该逻辑基于互连的一个或多个操作条件自适应地优化要终止的行数。 还公开了其他实施例。

公开(公告)号：US20160080007A1

公开(公告)日：2016-03-17

申请号：US14483486

申请日：2014-09-11

Applicant: Intel Corporation

Inventor： KHANG CHOONG YONG ,  BOON PING KOH ,  AMIT KUMAR SRIVASTAVA ,  WIL CHOON SONG

IPC: H04B1/04

CPC classification number: H04B1/0475 ,  H03F1/34 ,  H03F3/24 ,  H04B1/0483 ,  H04B3/30 ,  H04B15/02 ,  H04B2001/0408 ,  H04B2001/0433 ,  H04B2215/00

Abstract: Described is an apparatus which comprises: a pre-driver coupled to a transmitter, the transmitter having a differential output; and a tuning circuit operable to couple to the differential output to tune the pre-driver of the transmitter according to a common mode noise signature of a common mode signal derived from the differential output.

Abstract translation: 描述了一种装置，包括：耦合到发射机的预驱动器，所述发射机具有差分输出; 以及调谐电路，其可操作以耦合到差分输出端，以根据从差分输出得到的共模信号的共模噪声特征来调谐发射机的预驱动器。