公开(公告)号：US20220165677A1

公开(公告)日：2022-05-26

申请号：US17105416

申请日：2020-11-25

Applicant: Intel Corporation

Inventor： Grant Kloster ,  Robert Bristol

IPC: H01L23/544 ,  H01L23/528 ,  H01L21/027

Abstract: Integrated circuitry comprising an opaque material layer, such an interconnect metallization layer is first patterned with a maskless lithography to reveal an alignment feature, and is then patterned with masked lithography that aligns to the alignment feature. In some examples, the maskless lithography employs an I-line digital light processing (DLP) lithography system. In some examples the I-line DLP lithography system performs an alignment with IR illumination through a backside of a wafer. The maskless pattern may include dimensionally large windows within a frame around circuitry regions. A first etch of the opaque material layer may expose the alignment feature within the window, and a second etch of the opaque material may form IC features, such as interconnect metallization features.

公开(公告)号：US10756215B2

公开(公告)日：2020-08-25

申请号：US16271226

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Grant Kloster ,  Scott B. Clendenning ,  Rami Hourani ,  Szuya S. Liao ,  Patricio E. Romero ,  Florian Gstrein

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L29/06 ,  H01L29/786 ,  H01L21/31 ,  H01L23/498 ,  H01L21/32 ,  H01L29/423

Abstract: Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.

公开(公告)号：US10243080B2

公开(公告)日：2019-03-26

申请号：US15527288

申请日：2014-12-19

Applicant: INTEL CORPORATION

Inventor： Grant Kloster ,  Scott B. Clendenning ,  Rami Hourani ,  Szuya S. Liao ,  Patricio E. Romero ,  Florian Gstrein

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L29/06 ,  H01L29/786 ,  H01L21/32 ,  H01L23/498

Abstract: Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.

公开(公告)号：US12165987B2

公开(公告)日：2024-12-10

申请号：US17105416

申请日：2020-11-25

Applicant: Intel Corporation

Inventor： Grant Kloster ,  Robert Bristol

IPC: H01L23/544 ,  H01L21/027 ,  H01L23/528

Abstract: Integrated circuitry comprising an opaque material layer, such an interconnect metallization layer is first patterned with a maskless lithography to reveal an alignment feature, and is then patterned with masked lithography that aligns to the alignment feature. In some examples, the maskless lithography employs an I-line digital light processing (DLP) lithography system. In some examples the I-line DLP lithography system performs an alignment with IR illumination through a backside of a wafer. The maskless pattern may include dimensionally large windows within a frame around circuitry regions. A first etch of the opaque material layer may expose the alignment feature within the window, and a second etch of the opaque material may form IC features, such as interconnect metallization features.

公开(公告)号：US20240113039A1

公开(公告)日：2024-04-04

申请号：US17957552

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Tayseer Mahdi ,  Grant Kloster ,  Florian Gstrein

IPC: H01L23/00 ,  H01L21/02 ,  H01L23/29

CPC classification number: H01L23/562 ,  H01L21/02126 ,  H01L21/0217 ,  H01L23/291

Abstract: Methods, device structures, and wafer treatment chemistries related to backside wafer treatments to reduce distortions and overlay errors due to wafer deformation during wafer chucking are described. A backside layer is applied to the wafer prior to chucking. The chemistry of the backside layer lowers the surface free energy of the wafer during chucking to eliminate or mitigate wafer deformation during wafer processing.