公开(公告)号：US20240429301A1

公开(公告)日：2024-12-26

申请号：US18341467

申请日：2023-06-26

Applicant: Intel Corporation

Inventor： Rachel A. Steinhardt ,  Dmitri Evgenievich Nikonov ,  Kevin P. O'Brien ,  John J. Plombon ,  Tristan A. Tronic ,  Ian Alexander Young ,  Matthew V. Metz ,  Marko Radosavljevic ,  Carly Rogan ,  Brandon Holybee ,  Raseong Kim ,  Punyashloka Debashis ,  Dominique A. Adams ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Gauri Auluck ,  Scott B. Clendenning ,  Pratyush P. Buragohain

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: A transistor device may be formed with a doped perovskite material as a channel region. The doped perovskite material may be formed via an epitaxial growth process from a seed layer, and the channel regions of the transistor device may be formed from lateral overgrowth from the epitaxial growth process.

公开(公告)号：US20240222428A1

公开(公告)日：2024-07-04

申请号：US18091206

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Chelsey Dorow ,  Carl H. Naylor ,  Kirby Maxey ,  Kevin O'Brien ,  Ashish Verma Penumatcha ,  Chia-Ching Lin ,  Uygar Avci ,  Matthew Metz ,  Sudarat Lee ,  Ande Kitamura ,  Scott B. Clendenning ,  Mahmut Sami Kavrik

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/04 ,  H01L29/08 ,  H01L29/22 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/22 ,  H01L29/778 ,  H01L29/78696

Abstract: A transistor has multiple channel regions coupling source and drain structures, and a seed material is between one of the source or drain structures and a channel material, which includes a metal and a chalcogen. Each channel region may include a nanoribbon. A nanoribbon may have a monocrystalline structure and a thickness of a monolayer, less than 1 nm. A nanoribbon may be free of internal grain boundaries. A nanoribbon may have an internal grain boundary adjacent an end opposite the seed material. The seed material may directly contact the first of the source or drain structures, and the channel material may directly contact the second of the source or drain structures.

公开(公告)号：US20230420364A1

公开(公告)日：2023-12-28

申请号：US17849207

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Tristan A. Tronic ,  Ande Kitamura ,  Ashish Verma Penumatcha ,  Carl Hugo Naylor ,  Chelsey Dorow ,  Kirby Maxey ,  Scott B. Clendenning ,  Sudarat Lee ,  Uygar E. Avci

IPC: H01L23/528 ,  H01L23/522 ,  H01L29/423 ,  H01L29/18 ,  H01L27/092 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L29/42392 ,  H01L29/18 ,  H01L27/0924 ,  H01L29/78696 ,  H01L29/66742

Abstract: A microelectronic device, a semiconductor package including the device, an IC device assembly including the package, and a method of making the device. The device includes a substrate; a first structure on the substrate, the first structure corresponding to a front end of line (FEOL) stack of the device and including a plurality of first transistors therein; and a second structure on the substrate, the second structure corresponding to a back end of line (BEOL) stack of the device, and including a plurality of second transistors therein, the plurality of second transistors including a transition metal dichalcogenide (TMD) material. The second transistors are part of a voltage regulation architecture to regulate voltage supply to the die.

公开(公告)号：US20230187553A1

公开(公告)日：2023-06-15

申请号：US17546461

申请日：2021-12-09

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Gilbert W. Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Scott B. Clendenning ,  Jason C. Retasket ,  Edward O. Johnson, JR.

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L29/78696 ,  H01L29/66742

Abstract: Described herein are integrated circuit devices with source and drain (S/D) contacts with barrier regions. The S/D contacts conduct current to and from semiconductor devices, e.g., to the source and drain regions of a transistor. The barrier regions are formed between the S/D region and an inner conductive structure and reduce the Schottky barrier height between the S/D region and the contact. The barrier regions may include one or more carbon layers and one or more metal layers. A metal layer may include niobium, tantalum, aluminum, or titanium.

公开(公告)号：US11270887B2

公开(公告)日：2022-03-08

申请号：US16637177

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Patricio E. Romero ,  Scott B. Clendenning ,  Florian Gstrein ,  Cen Tan

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L29/51

Abstract: Embodiments herein describe techniques for a semiconductor device including a Ge substrate. A passivation layer may be formed above the Ge substrate, where the passivation layer may include one or more molecular monolayers with atoms of one or more group 15 elements or group 16 elements. In addition, a low-k interlayer may be above the passivation layer, and a high-k interlayer may be above the low-k interlayer. Furthermore, a metal contact may be above the high-k interlayer. Other embodiments may be described and/or claimed.

公开(公告)号：US11227798B2

公开(公告)日：2022-01-18

申请号：US16326135

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Scott B. Clendenning ,  Florian Gstrein

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285

Abstract: Disclosed are electronic device assemblies, computing devices, and related methods. An electronic device assembly or a computing device includes an interlayer dielectric region between a first region and a second region, a conductive interlayer structure formed through the interlayer dielectric region, and a barrier region formed around the conductive interlayer structure. The conductive interlayer structure includes a composition of Ml-Alm—X1n—X2p—Cq—Or, wherein M comprises a metal selected from one or more of titanium, zirconium, hafnium, tantalum, niobium and vanadium; C comprises carbon; O comprises oxygen; X1 comprises gallium; X2 comprises indium; and l, m, n, p, q and r represent an atomic percent of an element in the barrier region that can be 0 percent, but n and p cannot both be 0 percent. A method includes forming the barrier region within a passage through the interlayer dielectric region.

公开(公告)号：US10971600B2

公开(公告)日：2021-04-06

申请号：US16517220

申请日：2019-07-19

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Szuya S. Liao ,  Florian Gstrein ,  Rami Hourani ,  Patricio E. Romero ,  Grant M. Kloster ,  Martin M. Mitan

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/304 ,  H01L29/161 ,  H01L29/06 ,  H01L21/265 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775 ,  H01L21/28 ,  H01L29/49 ,  H01L21/266

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

公开(公告)号：US10396176B2

公开(公告)日：2019-08-27

申请号：US15506101

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Szuya S. Liao ,  Florian Gstrein ,  Rami Hourani ,  Patricio E. Romero ,  Grant M. Kloster ,  Martin M. Mitan

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/304 ,  H01L29/161 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775 ,  H01L29/06 ,  H01L21/28 ,  H01L29/49 ,  H01L21/265 ,  H01L21/266

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

公开(公告)号：US09786559B2

公开(公告)日：2017-10-10

申请号：US15044976

申请日：2016-02-16

Applicant: INTEL CORPORATION

Inventor： Paul A. Zimmerman ,  Scott B. Clendenning ,  Patricio E. Romero ,  Paul B. Fischer ,  Robert Edgeworth

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/64 ,  H01L23/48 ,  H01L25/065 ,  H01L21/02 ,  H01L23/60

CPC classification number: H01L21/76898 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76837 ,  H01L21/76841 ,  H01L21/76871 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/60 ,  H01L23/642 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrW2O8) or hafnium tungstate (HfW2O8). In some cases, the NTE material is disposed between the substrate and conductive core material of the TSV and serves to offset, at least in part, the coefficient of thermal expansion (CTE) mismatch there between, thus reducing heat-induced stresses and/or protrusion (pumping) of the conductive core material. The NTE material also may protect against leakage, voltage breakdown, and/or diffusion of the conductive core material. Furthermore, the NTE material may reduce radial stresses in high-aspect-ratio TSVs. In some cases, techniques disclosed herein may improve TSV reliability, enhance three-dimensional integration, and/or enhance performance in three-dimensional integrated circuits and/or other three-dimensional packages. Other embodiments which can employ techniques described herein will be apparent in light of this disclosure.

公开(公告)号：US09530733B2

公开(公告)日：2016-12-27

申请号：US14909736

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Robert L. Bristol ,  James M. Blackwell ,  Scott B. Clendenning ,  Florian Gstrein ,  Eungnak Han ,  Grant M. Kloster ,  Jeanette M. Roberts ,  Patricio E. Romero ,  Rami Hourani

IPC: H01L23/58 ,  H01L23/528 ,  H01L21/32 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/532 ,  H01L21/321

CPC classification number: H01L23/528 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/311 ,  H01L21/32 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.

Abstract translation: 一个方面的方法包括通过通过选择性化学反应分别形成第一多个较薄层中的每一个，在具有第一表面材料的第一区域上形成第一材料的第一较厚层。 该方法还包括限制在与第一区域相邻的第二区域上的第一多个较薄层中的每一个的侵入。 在第二区域上形成第二较厚的第二材料层，其具有不同于第一表面材料的第二表面材料。