公开(公告)号：US20230097793A1

公开(公告)日：2023-03-30

申请号：US17485331

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Pei-hua Wang ,  Gregory J. George ,  Bernhard Sell ,  Juan G. Alzate-Vinasco ,  Chieh-Jen Ku ,  Alekhya Nimmagadda

IPC: H01L29/45 ,  H01L29/24 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/443 ,  H01L29/66 ,  H01L27/108

Abstract: Described herein are integrated circuit devices with lined interconnects. Interconnect liners can help maintain conductivity between semiconductor devices (e.g., transistors) and the interconnects that conduct current to and from the semiconductor devices. In some embodiments, metal interconnects are lined with a tungsten liner. Tungsten liners may be particularly useful with semiconductor devices that use certain channel materials, such as indium gallium zinc oxide.

公开(公告)号：US20220415896A1

公开(公告)日：2022-12-29

申请号：US17358930

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Juan G. Alzate-Vinasco ,  Travis W. LaJoie ,  Wilfred Gomes ,  Fatih Hamzaoglu ,  Pulkit Jain ,  James Waldemer ,  Mark Armstrong ,  Bernhard Sell ,  Pei-Hua Wang ,  Chieh-Jen Ku

IPC: H01L27/108 ,  H01L29/786 ,  H01L29/66

Abstract: A device structure includes transistors on a first level in a first region and a first plurality of capacitors on a second level, above the first level, where a first electrode of the individual ones of the first plurality of capacitors are coupled with a respective transistor. The device structure further includes a second plurality of capacitors on the second level in a second region adjacent the first region, where individual ones of the second plurality of capacitors include a second electrode, a third electrode and an insulator layer therebetween, where the second electrode of the individual ones of the plurality of capacitors are coupled with a first interconnect on a third level above the second level, and where the third electrode of the individual ones of the plurality of capacitors are coupled with a second interconnect.

公开(公告)号：US20220208770A1

公开(公告)日：2022-06-30

申请号：US17696945

申请日：2022-03-17

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek A. Sharma ,  Tahir Ghani ,  Allen B. Gardiner ,  Travis W. Lajoie ,  Pei-hua Wang ,  Chieh-Jen Ku ,  Bernhard Sell ,  Juan G. Alzate-Vinasco ,  Blake C. Lin

IPC: H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L27/12

Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.

公开(公告)号：US20230171936A1

公开(公告)日：2023-06-01

申请号：US18161915

申请日：2023-01-31

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu ,  Bernhard Sell ,  Pei-hua Wang ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Umut Arslan ,  Travis W. Lajoie ,  Chieh-jen Ku

IPC: H10B10/00 ,  G11C11/403 ,  H10B12/00

CPC classification number: H10B10/00 ,  G11C11/403 ,  H10B12/01

Abstract: Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US11616192B2

公开(公告)日：2023-03-28

申请号：US16024599

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tofizur Rahman ,  Christopher J. Wiegand ,  Justin S. Brockman ,  Daniel G. Ouellette ,  Angeline K. Smith ,  Andrew Smith ,  Pedro A. Quintero ,  Juan G. Alzate-Vinasco ,  Oleg Golonzka

IPC: H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/10

Abstract: A memory device includes a perpendicular magnetic tunnel junction (pMTJ) stack, between a bottom electrode and a top electrode. In an embodiment, the pMTJ includes a fixed magnet, a tunnel barrier above the fixed magnet and a free magnet structure on the tunnel barrier. The free magnet structure includes a first free magnet on the tunnel barrier and a second free magnet above the first free magnet, wherein at least a portion of the free magnet proximal to an interface with the free magnet includes a transition metal. The free magnet structure having a transition metal between the first and the second free magnets advantageously improves the switching efficiency of the MTJ, while maintaining a thermal stability of at least 50 kT.

公开(公告)号：US11450669B2

公开(公告)日：2022-09-20

申请号：US16043548

申请日：2018-07-24

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu ,  Bernhard Sell ,  Pei-hua Wang ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Umut Arslan ,  Travis W. Lajoie ,  Chieh-jen Ku

IPC: H01L27/108 ,  G11C7/06 ,  G11C11/407 ,  H01L23/00 ,  H01L25/065 ,  H01L27/06 ,  H01L29/417 ,  H01L29/786 ,  H01L27/11

Abstract: Described herein are arrays of embedded dynamic random-access memory (eDRAM) cells that use TFTs as selector transistors. When at least some selector transistors are implemented as TFTs, different eDRAM cells may be provided in different layers above a substrate, enabling a stacked architecture. An example stacked TFT based eDRAM includes one or more memory cells provided in a first layer over a substrate and one or more memory cells provided in a second layer, above the first layer, where at least the memory cells in the second layer, but preferably the memory cells in both the first and second layers, use TFTs as selector transistors. Stacked TFT based eDRAM allows increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US20230067765A1

公开(公告)日：2023-03-02

申请号：US17409877

申请日：2021-08-24

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Noriyuki Sato ,  Van H. Le ,  Sarah Atanasov ,  Hui Jae Yoo ,  Bernhard Sell ,  Pei-hua Wang ,  Travis W. Lajoie ,  Chieh-Jen Ku ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu

IPC: H01L23/00 ,  H01L25/065

Abstract: IC devices implementing bilayer stacking with lines shared between bottom and top memory layers, and associated systems and methods, are disclosed. An example IC device includes a support structure, a front end of line (FEOL) layer and a back end of line (BEOL) layer. The BEOL layer includes a first memory cell in a first layer over the support structure, an electrically conductive line in a second layer, above the first layer, and a second memory cell in a third layer, above the second layer. The line could be one of a wordline, a bitline, or a plateline that is shared between the first and second memory cells. In particular, bilayer stacking line sharing is such that only one line is provided as a line to be shared between one or more of the memory cells of the first layer and one or more memory cells of the third layer.

公开(公告)号：US20220415897A1

公开(公告)日：2022-12-29

申请号：US17358954

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Juan G. Alzate-Vinasco ,  Travis W. LaJoie ,  Elliot N. Tan ,  Kimberly Pierce ,  Shem Ogadhoh ,  Abhishek A. Sharma ,  Bernhard Sell ,  Pei-Hua Wang ,  Chieh-Jen Ku

IPC: H01L27/108 ,  H01L29/786 ,  H01L29/66

Abstract: A device structure includes a first interconnect line along a longitudinal direction and a second interconnect line parallel to the first interconnect line, where the first interconnect structure is within a first metallization level and the second interconnect line is within a second metallization level. A first transistor and a laterally separated second transistor are on a same plane above the second interconnect line, where a gate of the first transistor is coupled to the first interconnect line and a gate of the second transistor is coupled to the second interconnect line. A first capacitor is coupled to a first terminal of the first transistor and a second capacitor is coupled to a first terminal of the second transistor. A third interconnect line couples a second terminal of the first transistor with a second terminal of the second transistor.

公开(公告)号：US20200035683A1

公开(公告)日：2020-01-30

申请号：US16043548

申请日：2018-07-24

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu ,  Bernhard Sell ,  Pei-hua Wang ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Umut Arslan ,  Travis W. Lajoie ,  Chieh-jen Ku

IPC: H01L27/108 ,  H01L27/06 ,  H01L25/065 ,  H01L29/786 ,  H01L23/00 ,  H01L29/417 ,  G11C11/407 ,  G11C7/06

Abstract: Described herein are arrays of embedded dynamic random-access memory (eDRAM) cells that use TFTs as selector transistors. When at least some selector transistors are implemented as TFTs, different eDRAM cells may be provided in different layers above a substrate, enabling a stacked architecture. An example stacked TFT based eDRAM includes one or more memory cells provided in a first layer over a substrate and one or more memory cells provided in a second layer, above the first layer, where at least the memory cells in the second layer, but preferably the memory cells in both the first and second layers, use TFTs as selector transistors. Stacked TFT based eDRAM allows increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US20190326296A1

公开(公告)日：2019-10-24

申请号：US15956379

申请日：2018-04-18

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek A. Sharma ,  Tahir Ghani ,  Allen B. Gardiner ,  Travis W. Lajoie ,  Pei-hua Wang ,  Chieh-jen Ku ,  Bernhard Sell ,  Juan G. Alzate-Vinasco ,  Blake C. Lin

IPC: H01L27/108 ,  H01L27/12 ,  H01L23/528 ,  H01L23/522 ,  H01L27/06

Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.