公开(公告)号：US11690212B2

公开(公告)日：2023-06-27

申请号：US16457610

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Umut Arslan ,  Juan G. Alzate Vinasco ,  Fatih Hamzaoglu

IPC: H01L21/768 ,  H10B12/00 ,  H01L27/12 ,  G11C11/407

CPC classification number: H10B12/315 ,  H01L27/124 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1255 ,  H10B12/0335 ,  G11C11/407

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first set of memory cells and a first selector are formed within a first group of metal layers and inter-level dielectric (ILD) layers above the substrate. A second set of memory cells and a second selector are formed within a second group of metal layers and ILD layers above the first group of metal layers and ILD layers. The first selector is coupled to the first set of memory cells to select one or more memory cells of the first set of memory cells based on a first control signal. In addition, the second selector is coupled to the second set of memory cells to select one or more memory cells of the second set of memory cells based on a second control signal. Other embodiments may be described and/or claimed.

公开(公告)号：US20230171936A1

公开(公告)日：2023-06-01

申请号：US18161915

申请日：2023-01-31

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu ,  Bernhard Sell ,  Pei-hua Wang ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Umut Arslan ,  Travis W. Lajoie ,  Chieh-jen Ku

IPC: H10B10/00 ,  G11C11/403 ,  H10B12/00

CPC classification number: H10B10/00 ,  G11C11/403 ,  H10B12/01

Abstract: Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US11610894B2

公开(公告)日：2023-03-21

申请号：US16457657

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek A. Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Gregory George ,  Akash Garg ,  Julie Rollins ,  Allen B. Gardiner ,  Shem Ogadhoh ,  Juan G. Alzate Vinasco ,  Umut Arslan ,  Fatih Hamzaoglu ,  Nikhil Mehta ,  Yu-Wen Huang ,  Shu Zhou

IPC: H01L27/108

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

公开(公告)号：US11450669B2

公开(公告)日：2022-09-20

申请号：US16043548

申请日：2018-07-24

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu ,  Bernhard Sell ,  Pei-hua Wang ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Umut Arslan ,  Travis W. Lajoie ,  Chieh-jen Ku

IPC: H01L27/108 ,  G11C7/06 ,  G11C11/407 ,  H01L23/00 ,  H01L25/065 ,  H01L27/06 ,  H01L29/417 ,  H01L29/786 ,  H01L27/11

Abstract: Described herein are arrays of embedded dynamic random-access memory (eDRAM) cells that use TFTs as selector transistors. When at least some selector transistors are implemented as TFTs, different eDRAM cells may be provided in different layers above a substrate, enabling a stacked architecture. An example stacked TFT based eDRAM includes one or more memory cells provided in a first layer over a substrate and one or more memory cells provided in a second layer, above the first layer, where at least the memory cells in the second layer, but preferably the memory cells in both the first and second layers, use TFTs as selector transistors. Stacked TFT based eDRAM allows increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US20200005866A1

公开(公告)日：2020-01-02

申请号：US16023728

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Pulkit Jain ,  Umut Arslan ,  Fatih Hamzaoglu

IPC: G11C13/00 ,  G11C7/06 ,  G11C8/10

Abstract: Some embodiments include apparatuses having a resistive memory device and methods to apply a combination of voltage stepping current stepping and pulse width stepping during an operation of changing a resistance of a memory cell of the resistive memory device. The apparatuses also include a write termination circuit to limit drive current provided to a memory cell of the resistive memory device during a particular time of an operation performed on the memory cell. The apparatuses further include a programmable variable resistor and resistor control circuit that operate during sensing operation of the memory device.

公开(公告)号：US09865322B2

公开(公告)日：2018-01-09

申请号：US15280935

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Cyrille Dray ,  Blake C. Lin ,  Fatih Hamzaoglu ,  Liqiong Wei ,  Yih Wang

IPC: G11C11/16 ,  G06F3/06

CPC classification number: G11C11/1675 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/067 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697

Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.

公开(公告)号：US11832438B2

公开(公告)日：2023-11-28

申请号：US16457634

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek A. Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Gregory George ,  Akash Garg ,  Allen B. Gardiner ,  Shem Ogadhoh ,  Juan G. Alzate Vinasco ,  Umut Arslan ,  Fatih Hamzaoglu ,  Nikhil Mehta ,  Jared Stoeger ,  Yu-Wen Huang ,  Shu Zhou

IPC: H10B12/00 ,  H01L27/12 ,  H01L49/02

CPC classification number: H10B12/315 ,  H01L27/124 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1255 ,  H01L28/55 ,  H01L28/65 ,  H01L28/82 ,  H10B12/0335 ,  H10B12/312

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US10438640B2

公开(公告)日：2019-10-08

申请号：US16052552

申请日：2018-08-01

Applicant: Intel Corporation

Inventor： Liqiong Wei ,  Fatih Hamzaoglu ,  Yih Wang ,  Nathaniel J. August ,  Blake C. Lin ,  Cyrille Dray

IPC: G11C11/16 ,  G11C29/02 ,  G11C13/00

Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

公开(公告)号：US10068628B2

公开(公告)日：2018-09-04

申请号：US14129277

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Liqiong Wei ,  Fatih Hamzaoglu ,  Yih Wang ,  Nathaniel J. August ,  Blake C. Lin ,  Cyrille Dray

IPC: G11C11/16 ,  G11C29/02 ,  G11C13/00

Abstract: Apparatuses for improving resistive memory energy efficiency are provided. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

公开(公告)号：US09666268B2

公开(公告)日：2017-05-30

申请号：US14703723

申请日：2015-05-04

Applicant: Intel Corporation

Inventor： Yih Wang ,  Muhammad M. Khellah ,  Fatih Hamzaoglu

IPC: G11C7/00 ,  G11C11/419 ,  G11C5/14 ,  G11C11/4074

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C5/148 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417

Abstract: Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.