公开(公告)号：US20210303357A1

公开(公告)日：2021-09-30

申请号：US16833595

申请日：2020-03-28

Applicant: Intel Corporation

Inventor： Ankush VARMA ,  Nikhil GUPTA ,  Vasudevan SRINIVASAN ,  Krishnakanth SISTLA ,  Nilanjan PALIT ,  Abhinav KARHU ,  Eugene GORBATOV ,  Eliezer WEISSMANN

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54 ,  G06F15/80

Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores to be allocated to form a first plurality of logical processors (LPs) to execute threads, wherein one or more logical processors (LPs) are to be associated with each core of the plurality of cores; scheduling guide circuitry to: monitor execution characteristics of the first plurality of LPs and the threads; generate a first plurality of LP rankings, each LP ranking including all or a subset of the plurality of LPs in a particular order; and store the first plurality of LP rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of LPs using the first plurality of LP rankings; a power controller to execute power management code to perform power management operations including independently adjusting frequencies and/or voltages of one or more of the plurality of cores; wherein in response to a core configuration command to deactivate a first core of the plurality of cores, the power controller or privileged program code executed on the processor are to update the memory with an indication of deactivation of the first core, wherein responsive to the indication of deactivation of the first core, the scheduler is to modify the scheduling of the threads.

公开(公告)号：US20250076954A1

公开(公告)日：2025-03-06

申请号：US18883276

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Vivek GARG ,  Ankush VARMA ,  Krishnakanth SISTLA ,  Nikhil GUPTA ,  Nikethan Shivanand BALIGAR ,  Stephen WANG ,  Nilanjan PALIT ,  Timothy Yee-Kwong KAM ,  Adwait PURANDARE ,  Ujjwal GUPTA ,  Stanley CHEN ,  Dorit SHAPIRA ,  Shruthi VENUGOPAL ,  Suresh CHEMUDUPATI ,  Rupal PARIKH ,  Eric DEHAEMER ,  Pavithra SAMPATH ,  Phani Kumar KANDULA ,  Yogesh BANSAL ,  Dean MULLA ,  Michael TULANOWSKI ,  Stephen Paul HAAKE ,  Andrew HERDRICH ,  Ripan DAS ,  Nazar Syed HAIDER ,  Aman SEWANI

IPC: G06F1/28 ,  G06F1/30 ,  G06F13/20

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

公开(公告)号：US20220244996A1

公开(公告)日：2022-08-04

申请号：US17717859

申请日：2022-04-11

Applicant: INTEL CORPORATION

Inventor： Ankush VARMA ,  Nikhil GUPTA ,  Vasudevan SRINIVASAN ,  Krishnakanth SISTLA ,  Nilanjan PALIT ,  Abhinav KARHU ,  Eugene GORBATOV ,  Eliezer WEISSMANN

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54 ,  G06F15/80

Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.