公开(公告)号：US20250076954A1

公开(公告)日：2025-03-06

申请号：US18883276

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Vivek GARG ,  Ankush VARMA ,  Krishnakanth SISTLA ,  Nikhil GUPTA ,  Nikethan Shivanand BALIGAR ,  Stephen WANG ,  Nilanjan PALIT ,  Timothy Yee-Kwong KAM ,  Adwait PURANDARE ,  Ujjwal GUPTA ,  Stanley CHEN ,  Dorit SHAPIRA ,  Shruthi VENUGOPAL ,  Suresh CHEMUDUPATI ,  Rupal PARIKH ,  Eric DEHAEMER ,  Pavithra SAMPATH ,  Phani Kumar KANDULA ,  Yogesh BANSAL ,  Dean MULLA ,  Michael TULANOWSKI ,  Stephen Paul HAAKE ,  Andrew HERDRICH ,  Ripan DAS ,  Nazar Syed HAIDER ,  Aman SEWANI

IPC: G06F1/28 ,  G06F1/30 ,  G06F13/20

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

公开(公告)号：US20200210332A1

公开(公告)日：2020-07-02

申请号：US16816779

申请日：2020-03-12

Applicant: Intel Corporation

Inventor： Ian M. STEINER ,  Andrew J. HERDRICH ,  Wenhui SHU ,  Ripan DAS ,  Dianjun SUN ,  Nikhil GUPTA ,  Shruthi VENUGOPAL

IPC: G06F12/06 ,  G06F11/30 ,  G06F11/34

Abstract: Examples include a computing system for receiving memory class of service parameters; setting performance monitoring configuration parameters, based at least in part on the memory class of service parameters, for use by a performance monitor of a memory controller to generate performance monitoring statistics by monitoring performance of one or more workloads by a plurality of processor cores based at least in part on the performance monitoring configuration parameters; receiving the performance monitoring statistics from the performance monitor; and generating, based at least in part on the performance monitoring statistics, a plurality of memory bandwidth settings to be applied by a memory bandwidth allocator to the plurality of processor cores to dynamically adjust priorities of memory bandwidth allocated for the one or more workloads to be processed by the plurality of processor cores.

公开(公告)号：US20190384348A1

公开(公告)日：2019-12-19

申请号：US16480830

申请日：2017-02-24

Applicant: INTEL CORPORATION

Inventor： Vasudevan SRINIVASAN ,  Krishnakanth V. SISTLA ,  Corey D. GOUGH ,  Ian M. STEINER ,  Nikhil GUPTA ,  Vivek GARG ,  Ankush VARMA ,  Sujal A. VORA ,  David P. LERNER ,  Joseph M. SULLIVAN ,  Nagasubramanian GURUMOORTHY ,  William J. BOWHILL ,  Venkatesh RAMAMURTHY ,  Chris MACNAMARA ,  John J. BROWNE ,  Ripan DAS

IPC: G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.