公开(公告)号：US09984737B2

公开(公告)日：2018-05-29

申请号：US15354200

申请日：2016-11-17

Applicant: INTEL CORPORATION

Inventor： Christopher E. Cox ,  Kuljit Singh Bains ,  John B. Halbert

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4096 ,  G11C11/4074 ,  G11C7/08

CPC classification number: G11C11/40615 ,  G11C7/00 ,  G11C7/08 ,  G11C11/40611 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4096 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C2211/4065 ,  G11C2211/4068

Abstract: Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

公开(公告)号：US09536588B2

公开(公告)日：2017-01-03

申请号：US15181358

申请日：2016-06-13

Applicant: INTEL CORPORATION

Inventor： Christopher E. Cox ,  Kuljit Singh Bains ,  John B. Halbert

IPC: G11C16/24 ,  G11C11/406 ,  G11C11/409 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C11/40615 ,  G11C7/00 ,  G11C7/08 ,  G11C11/40611 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4096 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C2211/4065 ,  G11C2211/4068

Abstract: Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

Abstract translation: 设备，系统和方法包括适应存储器件的读/写操作和自刷新模式的主动模式，以适应当读/写操作空闲时表示存储数据的电压电平的再充电。 至少一个寄存器源提供小于第一电压电平的第一电压电平和第二电压电平。 通过这样的配置，在活动模式期间，存储器件以由至少一个寄存器源提供的第一电压电平工作，并且在自刷新模式期间，存储器件以由第二电压电平 至少一个寄存器源。

公开(公告)号：US08775991B2

公开(公告)日：2014-07-08

申请号：US13888627

申请日：2013-05-07

Applicant: Intel Corporation

Inventor： Michael W. Leddige ,  Kuljit Singh Bains ,  John Thomas Sprietsma

IPC: G06F17/50

CPC classification number: H01L23/49816 ,  G11C5/02 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10734 ,  H05K2203/1572 ,  Y02P70/611

Abstract: A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate. Other embodiments are also disclosed and claimed.

Abstract translation: 存储器模块具有连接阵列。 连接阵列以行和列排列，使得存在第一和第二外部列。 可以互换第一和第二外柱中的连接，以优化在基板上的双面模块放置。 还公开并要求保护其他实施例。