公开(公告)号：US20240202419A1

公开(公告)日：2024-06-20

申请号：US18538409

申请日：2023-12-13

Applicant: Intel Corporation

Inventor： Miaomiao Ma ,  Adam Norman ,  Jianfang Olena Zhu ,  Mackenzie Norman ,  Mark Gallina ,  Pei Chun Ch'ng ,  Xia Zhu ,  Jagadeesh Radhakrishnan ,  Soon Khiang Toh ,  Omer Vikinski ,  Slade Morgan

IPC: G06F30/392 ,  G06F30/27 ,  G06F115/02 ,  G06F119/08

CPC classification number: G06F30/392 ,  G06F30/27 ,  G06F2115/02 ,  G06F2119/08

Abstract: Systems, apparatuses and methods may provide for technology that determines a plurality of transient thermal responses for a corresponding plurality of power source locations on a semiconductor die, obtains corner block list (CBL) representations associated with a plurality of candidate floorplans, and conducts an artificial intelligence (AI) based search of the CBL representations, wherein an output of the AI based search is one or more suggested floorplans having a transient thermal response that is below a thermal threshold.

公开(公告)号：US10001822B2

公开(公告)日：2018-06-19

申请号：US14860854

申请日：2015-09-22

Applicant: Intel Corporation

Inventor： Assaf Ganor ,  Efraim Rotem ,  Noam Winer ,  Omer Vikinski

IPC: G06F1/18 ,  G06F1/26

CPC classification number: G06F1/26 ,  G05F1/46 ,  G06F1/18

Abstract: In one embodiment, a processor includes: a power switcher circuit to receive a first voltage and charge at least one charge storage device with the first voltage in a first phase and output charge in a second phase; a selection circuit coupled to the power switcher circuit to couple the output charge to a selected one of a plurality of load circuits responsive to a control signal; and a control circuit to generate the control signal based at least in part on a comparison of a feedback voltage of a rail coupled to the selected load circuit to a reference voltage. Other embodiments are described and claimed.

公开(公告)号：US20170083067A1

公开(公告)日：2017-03-23

申请号：US14860854

申请日：2015-09-22

Applicant: INTEL CORPORATION

Inventor： Assaf Ganor ,  Efraim Rotem ,  Noam Winer ,  Omer Vikinski

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G05F1/46 ,  G06F1/18

Abstract: In one embodiment, a processor includes: a power switcher circuit to receive a first voltage and charge at least one charge storage device with the first voltage in a first phase and output charge in a second phase; a selection circuit coupled to the power switcher circuit to couple the output charge to a selected one of a plurality of load circuits responsive to a control signal; and a control circuit to generate the control signal based at least in part on a comparison of a feedback voltage of a rail coupled to the selected load circuit to a reference voltage. Other embodiments are described and claimed.

公开(公告)号：US09996127B2

公开(公告)日：2018-06-12

申请号：US14207074

申请日：2014-03-12

Applicant: Intel Corporation

Inventor： Omer Vikinski ,  Igor Yanover ,  Gavri Berger ,  Gabi Malka ,  Zeev Sperber

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F9/50

CPC classification number: G06F1/26 ,  G06F1/28 ,  G06F1/329 ,  G06F9/5094 ,  Y02D10/24

Abstract: A processor and method are described for performing proactive throttling of execution unit ports. For example, one embodiment of a processor core comprises: a plurality of execution unit ports within an execution stage of the processor core; a scheduler unit to schedule execution of a plurality of operations to the plurality of execution unit ports; and proactive throttling logic to limit acceleration of execution of the operations by the ports to an acceleration level which does not result in significant power supply droops.